Analogue to digital converters

Coded data generation or conversion – Analog to digital conversion followed by digital to analog...

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Details

341159, 341156, H03M 100

Patent

active

048704164

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND TO INVENTION

The present invention relates to subranging analogue to digital converters.
A known subranging analogue to digital converter comprises a first analogue to digital converter for receiving an analogue input signal to be converted, connected in series to a digital to analogue converter the output of which is connected in series via an operational amplifier to the input of a second analogue to digital converter. One of the inputs of the operational amplifier is connected to the output of the digital to analogue converter and a second input of the operational amplifier is connected via a delay line to the input of the first analogue to digital converter. In operation, the operational amplifier subtracts the analogue input signal from the output of the digital to analogue converter to provide an "error" signal which is transmitted to the input of the second analogue to digital converter. At least a part of the digital output from the second analogue to digital converter is combined with the digital output from the first analogue to digital converter to provide the digital output signal of the subranging analogue to digital converter.
The speed and accuracy of convertion of the analogue input signal to the digital output signal in the above described subranging circuit is adversely affected by signal propagation delays within the digital to analogue converter and within the series connected operational amplifier. These two propagation delays act as a constraint on the frequency of operation and performance of the subranging circuit.


SUMMARY OF INVENTION

An objective of the present invention is to improve the frequency of operation and the performance of subranging analogue to digital converters.
According to the present invention there is provided a subranging analogue to digital converter comprising a first analogue to digital converter for receiving an analogue input signal to be converted, a digital to analogue converter the input of which is coupled in series to the output of the first analogue to digital converter, a second analogue to digital converter the input of which is coupled in series to the output of the digital to analogue converter wherein the improvement lies in the provision of a circuit arrangement, in parallel with the digital to analogue converter and the first analogue to digital converter, for inverting the analogue input signal to provide an inverted analogue signal and summing means for combining the inverted analogue signal with the output signal from the digital to analogue converter to provide an input signal for the second analogue to digital converter.
A fundamental principle is that of replacing the operation of subtraction in the known subranging circuits by two operations, inversion and addition in such a way that the inversion operation time delay is effected in parallel with the digital to analogue time delay whereby the time delay caused by subtraction is eliminated thereby greatly improving the performance of the subranging analogue to digital converter.
In a preferred embodiment of the present invention the circuit arrangement, in parallel with the digital to analogue converter, comprises an operational amplifier an input of which is coupled via a delay line to the input of the first analogue to digital converter, the output of the operational amplifier being coupled via a transistor to the output of the digital to analogue converter, the operational amplifier and the transistor serving in operation to provide the inverted analogue signal, by inverting the analogue input signal to be converted and effecting a voltage to current conversion.
In one embodiment the transistor is of p-n-p type from the collector of which is transmitted in operation the inverted analogue signal.
In the one embodiment in which the transistor is of p-n-p type the collector is coupled to the output of the digital to analogue converter, the base of the transistor is coupled to the output of the operational amplifier and the emitter of the transistor is coupled via a feedback

REFERENCES:
patent: 3891984 (1975-06-01), Kerwin et al.
patent: 4686511 (1987-08-01), Koen
patent: 4733217 (1988-03-01), Dingwall

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