Analogue to digital converter

Details Analogue to digital converter Analogue to digital converter

1999-09-27

2001-11-06

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S161000, C341S162000, C341S165000, C341S172000, C341S158000, C341S120000

Reexamination Certificate

active

06313780

ABSTRACT:

The invention relates to current mode pipelined analogue to digital (A/D) converters and to a single stage for use in such converters.
Such an A/D converter is disclosed in a paper entitled “A Full Nyquist 15 MS/s 8-b Differential Switched-Current A/D Converter” by Mark Bracey, William Redman-White, Judith Richardson, and John B. Hughes published in IEEE Journal of Solid State Circuits, Vol. 31, No. 7, July 1996. In the A/D converter disclosed each bit stage includes two current memory circuits in the signal path. This increases the transmission loss, noise, and power consumption.
A further A/D converter which also contains two current memory circuits in the signal path in each bit stage is disclosed in a paper entitled “A 10 Bit Pipelined Switched-Current A/D Converter” by D. Macq and P. G. A. Jespers published in IEEE Journal of Solid-State Circuits Vol. 29, No. 8, August 1994. This, of course, suffers the same disadvantages as that in the preceding paragraph.
A pipelined A/D converter is disclosed in a paper entitled “New Current-Mode Pipeline A/D Converter Architecture” by Mikael Gustavsson and Nianxiong Tan published in 1997 IEEE international Symposium on Circuits and Systems, Jun. 9-12 1977 in which each bit stage in the pipelined converter uses only a single current memory. In this arrangement a first generation switched current memory is used as the quantiser and the current memory of the next bit cell are time interleaved which makes it necessary to provide the output current in all clock phases.
It has been found that when a comparator circuit including a regenerative latching circuit is connected to the output of a current memory circuit it can cause a corruption of the current stored in the current memory. Thus if only a single current memory is used in a bit stage the current passed on to the next stage may be corrupted by the operation of the comparator. This is one factor which has caused designs to be proposed where two current memories per bit stage are used in the signal transmission path. As disclosed in the paper by Bracey et al the first current memory passes an uncorrupted current to the second current memory before the comparison takes place thus making any corruption of the current in the first current memory caused by the action of the comparator unimportant as the corrupted current is not further used after application to the comparator.
It is an object of the invention to enable the provision of a current mode pipelined A/D converter in which some or all of the problems involved with the prior art are reduced or eliminated.
The invention provides a current mode pipelined analogue to digital converter (ADC) comprising a plurality of serially connected conversion stages; in which each conversion stage comprises a current input for receiving a series of input current samples, a current output for producing a series of residual current samples, and a digital output for producing a digital signal representing the digital conversion performed by the stage, means for coupling the current input to the input of a first current memory circuit during a first portion of each sample conversion period, means for coupling the current input to the input of a second current memory circuit during a second portion of each sample conversion period, a current comparator having a first input coupled to the output of the first current memory circuit, a second input which receives a reference current, and an output coupled to the digital output and to the input of a digital to analogue converter (DAC), and current summing means having a first input coupled to the output of the second current memory circuit, a second input coupled to the output of the DAC, and an output coupled to the current output.
The use of two current memory stages in each conversion stage each of which sample the input current at different times and one of which passes on the sampled input current to the output of the conversion stage enables the transmission loss to be minimised without incurring the penalty of corruption of the current passed on to the next stage by comparator “kick back”. Thus in the arrangement according to the invention the current memory which is connected to the comparator plays no part in determining the current passed to the next stage, apart from enabling the comparator decision which controls the DAC, and consequently will not corrupt that current. Consequently any corruption of the current stored caused by comparator “Kick Back” is unimportant because the sample stored in the memory cell driving the comparator is not in the signal path and is discarded after the decision has been made.
Each conversion stage may produce one bit of the digital output of the ADC. This enables a simple DAC to be used which merely takes the output of a single comparator as its digital input. It would, of course, be possible to convert more than one bit per conversion stage, but this would require more complex circuitry, for example a plurality of comparators, a plurality of outputs from the first current memory (which could be provided using current mirror circuits), and a plurality of switched matched current sources in the DAC.
The output of the first current memory circuit may be applied to the first input of the comparator during the second portion of the sample period. This enables a minimum delay before the result of the comparison is available (and hence the digital output of the stage).
Each sample period may be divided into four phases wherein during a first phase the input current sample is sampled and stored in the first current memory, during a second phase the input current sample is sampled and stored in the second current memory and the output of the first current memory is fed to the first input of the comparator, during a third phase the result of the comparison is fed to the digital output as the result of the present conversion stage and to the input of the DAC and during a fourth and subsequent phase the output of the DAC and the second current memory are fed to the respective inputs of the summing means,the output of the summing means being coupled to the current output to provide the residual current output of the conversion stage.
It will be appreciated by those skilled in the art that in these circumstances each conversion stage will take only three of the phases to convert the input sample current and pass the residual sample current to the next conversion stage. Consequently the timing shifts by one phase of the sample period from stage to stage. This is of little consequence in that the deskewing logic is already present to reconcile the pipeline timing and this additional timing shift can easily be taken care of in that logic. One consequence is that the total time delay along the pipeline for an individual input sample is reduced to 75% of that where as whole sample period is used for each conversion stage.
Alternatively each sample period may be divided into four phases; wherein during a first and a second phase the input current sample is sampled and stored in the first current memory circuit, the output of the second current memory circuit is fed to the first input of the current summing means, the output of the DAC is fed to the second input of the current summing means, and the output of the current summing means is coupled to the current output to provide the residual current output of the conversion stage; during the third phase the input current sample is sampled and stored in the second current memory circuit and the output of the first current memory circuit is fed to the first input of the comparator; and during a fourth phase the result of the comparison is fed to the digital output as the digital conversion by the present conversion stage and to the input of the DAC, the output of the DAC and the second current memory are fed to the respective inputs of the summing means, and the output of the summing means is coupled to the current output to provide the residual current output of the conversion stage.
In this case each conversion stage takes all of th

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