Analogue to digital converter

Communications: electrical – Audible indication – Percussion-type sound producer

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Details

340347AD, 324 99D, H03K 1302

Patent

active

046493727

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to an analogue to digital converter for use in a PCM audio system and the like using a digital audio signal which is obtained by a pulse code modulation (PCM) technique.


TECHNICAL BACKGROUND

An analogue to digital converter of the counter type having characteristics high in accuracy has been frequenctly employed in audio systems such as a PCM audio system. Shown in FIG. 1 is a typical example of such a counter type analogue to digital converter. In FIG. 1, reference numeral 1 designates an integrator which is composed of an operational amplifier 1A and a capacitor 1B. An input terminal 3 is coupled through a sampling switch 2 to the input terminal of the integrator 1 together with a constant current source section 4. The sampling switch 2 is subjected to an ON-OFF control operation in response to a predetermined sampling pulse P.sub.s thereby to switch an input analogue signal applied to the input terminal 3. The integrator 1 is operative to carry out an integrating operation for the input analogue signal applied through the sampling switch 2. Further, both a constant current I.sub.0 from a first constant current source 4A and a constant current I.sub.1 from a second constant current source 4B are supplied to the integrator 1 through current switches 4C and 4D, respectively, to be integrated therein. The constant current sources 4A and 4B and the current switches 4C and 4D constitute the constant current source section 4. The constant currents I.sub.0 and I.sub.1 are determined to satisfy the relation of (I.sub.0 +I.sub.1)/I.sub.1 =2.sup.7 and I.sub.0 =127.multidot.I.sub.1. The output terminal of the integrator 1 is coupled to the input terminal of a comparing section 5.
The comparing section 5 is composed of a first comparator 5A, a second comparator 5B and a reference voltage source 5C. The output voltage of the integrator 1 is supplied to both comparison input terminals of the first and second comparator 5A and 5B, respectively. The reference voltage of the reference voltage source 5C is supplied to a reference input terminal of the first comparator 5A whereas a reference input terminal of the second comparator 5B is grounded. The output terminals of the first and second comparators 5A and 5B are connected to both a control section 6 and a counter section 7.
The control section 6 is operative to produce the above-described sampling pulse P.sub.s to be supplied to a control terminal of the sampling switch 2. Further, the control section 6 is operative to produce a control signal P.sub.1 to be supplied to control terminals of the first and second comparator 5A and 5B and to produce control signals P.sub.2 and P.sub.3 to be supplied to control terminals of the current switches 4C and 4D, respectively. A comparison output C.sub.1 of the first comparator 5A and a comparison output C.sub.2 of the second comparator 5B are supplied to the control section 6.
The counter section 7 includes a first counter 7A for higher bits and a second counter 7B for lower bits. A control signal C.sub.0 is supplied from the control section 6 to a start terminal of the first counter 7A and the comparison output C.sub.1 of the first comparator 5A is supplied to a stop terminal of the first counter 7A and a start terminal of the second counter 7B. Further, the comparison output C.sub.2 is supplied to a stop terminal of the second counter 7B.
The operation of the analogue to digital converter described above will be explained hereinafter with reference to the accompanying FIG. 2.
Now, when the input analogue signal is applied to the input terminal 3, during a period of time t.sub.0 to t.sub.1 shown in FIGS. 2A to 2H, the sampling pulse P.sub.s takes a high level as shown in FIG. 2A and this results in that the sampling switch 2 is turned on. Accordingly, the integration is carried out in accordance with the input analogue signal in the integrator 1, so that an output voltage V.sub.0 of the integrator 1 decreases as shown in FIG. 2B. This output voltage V.sub.0 corresponds to the level of th

REFERENCES:
patent: 3242327 (1966-03-01), Burk et al.
patent: 3476924 (1969-11-01), Conger
patent: 3749894 (1973-07-01), Avdeef
patent: 4024533 (1977-05-01), Neumann
patent: 4128885 (1978-12-01), Valek et al.
patent: 4268820 (1981-05-01), Hareyama
patent: 4270119 (1981-05-01), Mitamura
patent: 4342983 (1982-08-01), Weigand et al.
patent: 4404545 (1983-09-01), Nakanishi et al.

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