Analogue delay circuit with a constant delay time

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

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327309, H03H 1126

Patent

active

058617655

ABSTRACT:
In an analogue delay circuit which is constructed from a p-type MOS transistor and an n-type MOS transistor and which includes an inverter gate for inputting input signals and a capacitance having one electrode connected to ground and the other electrode connected to the drain of the inverter gate, the gate potential of the n-type MOS transistor is limited by means of a clamping circuit so as not to exceed the minimum operating voltage, and the potential of a line connected to an electrode of the capacitance is limited by another clamping circuit so as to not exceed the minimum operating voltage.

REFERENCES:
patent: 4792705 (1988-12-01), Ouyang et al.
patent: 4886986 (1989-12-01), Watanabe
patent: 4967099 (1990-10-01), Mori
patent: 5250854 (1993-10-01), Lien
patent: 5268600 (1993-12-01), Yeu

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