Analogue-controlled phase interpolator

Details Analogue-controlled phase interpolator Analogue-controlled phase interpolator

2001-02-23

2002-10-15

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C331S008000, C331S034000, C331S045000, C331S057000, C331S17700V, C327S156000, C327S159000, C375S376000

Reexamination Certificate

active

06466098

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the control of a phase interpolator circuit such as may be used to generate a data recovery clock signal from a pair of reference clocks.
2. Description of Related Art
In the general field of data transmission it is well known to need to generate, at a receiver, a clock signal in a well established phase relationship with the received data signal. This is used in the sampling or other processing of the received signal to recover the transmitted data. As transmission data rates increase it is ever more important to generate the data recovery clock signal with accuracy, and to have close control over its adjustment.
Our earlier application EP-A-0909035, which corresponds to U.S. Pat. No. 6,107,848 issued Aug. 22, 2000 and which is incorporated herein by reference, describes a phase synchronising arrangement, one possible use of which is the generation of a data recovery clock signal from a pair of quadrature related reference clock signals. Reference may be made to that application for a detailed discussion of the principles involved but an outline description is given in the following.
FIG. 1
is a phasor diagram illustrating the generation of a data recovery clock signal in a desired phase relationship to a pair of quadrature related reference clock signals CLK
1
, CLK
2
. If it is assumed that the desired clock signal should have a phase displacement of &thgr; from CLK
1
, then the desired signal can be expressed as cos &thgr;.CLK
1
+sin &thgr;.CLK
2
. In the particular example shown, &thgr;=150□ and so the desired signal is −0.87 CLK
1
+0.50 CLK
2
. It will be appreciated that any desired phase relationship can be generated by selection of suitable cos/sin pairs as the coefficients or weighting values for CLK
1
and CLK
2
. This is illustrated in
FIG. 2
where the weighting value for CLK
1
is designated W
1
and that for CLK
2
is W
2
, and pairs of W
1
, W
2
can be selected for desired values of the phase shift.
A schematic illustration of an implementation of a phase mixer to perform the above mixing is shown in FIG.
3
. In this diagram each signal is represented by a pair of signal lines. The phase mixer comprises four differential amplifiers
31
a
,
31
b
,
32
a
,
32
b
each of which includes two transistors as illustrated in a conventional fashion.
Reference clock CLK
1
is applied to amplifiers
31
a
,
31
b
with opposite polarities, such that one amplifier acts to add the reference clock to the sum signal, while the other subtracts it. The current sources I
1
p
I
1
n
control the extents to which the amplifiers add and subtract the reference signal. The current pair I
1
p
I
1
n
thus are equivalent to the differential circuit weighting W
1
enabling W
1
to be adjusted from +1 to −1. Correspondingly, CLK
2
is applied to amplifiers
32
a
,
32
b
and I
2
p,
I
2
n
are equivalent to W
2
.
EP-A-0909035 describes in detail how suitable values of I
1
p
I
1
n,
I
2
p,
I
2
n
may be generated from a selection of switched current sources of various values. That switching arrangement, and others, however can only provide a certain number of W
1
, W
2
pairs and hence the number of available phase shifts which can be selected is limited. This is illustrated in
FIG. 4
which corresponds to the arrangement described in EP-A-0909035 and shows a situation where 12 evenly spaced phase shifts are available.
Such systems, which use a digital control to switch a set of current sources to set the weighting values and hence the phase shift have some drawbacks however. Principally, in the context of increasing data rates as mentioned above, problems arise because the resolution of the recovery clock phase adjustment is limited by the control logic. Also, non-ideal behaviour of the phase interpolator itself means it is increasingly difficult to maintain phase step size linearity for fine degrees of timing.
SUMMARY OF THE INVENTION
The present invention provides an arrangement for the generation of the control signals for a phase interpolator, designated I
1
p
I
1
n,
I
2
p,
I
2
n
in the above, such that the control signals may be adjusted more finely. More particularly the invention provides signals which represent a cos/sin pair, the phase of which can be adjusted continuously, or in sufficiently small steps, such that, when input as the control signals to a phase interpolator, fine phase control of the output of the interpolator can be achieved.
The preferred circuit used to implement the invention is a variation of a ring oscillator circuit, configured such that it provides a pair of signals which correspond to a cos/sin pair, the phase of which can be adjusted to adjust the phase of the interpolator output.


REFERENCES:
patent: 6005448 (1999-12-01), Pickering et al.
patent: 6107848 (2000-08-01), Pickering et al.

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