Analog voltage address decoder circuit

Details Analog voltage address decoder circuit Analog voltage address decoder circuit

1995-04-14

1997-09-30

DeBoer, Todd E.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341133, H03M 136

Patent

active

056730489

ABSTRACT:
An analog voltage address decoder circuit and stackable voltage comparator circuit are provided. The address decoder circuit has a column decode comparator network made up of a first plurality of interconnected comparator circuits and a row decode comparator network made up of a second plurality of interconnected comparator circuits. The column decode comparator network compares a plurality of reference voltages with an analog input voltage so as to detect if the analog input voltage is within a bounded window. Likewise, the row decode comparator network compares an analog input voltage with a plurality of reference voltages to detect if the analog input voltage is within a bounded window. Detection within the proper bounded windows for the rows and columns produces a corresponding "high" binary output to a particular memory location for access thereto. The decode comparator networks use stackable voltage comparator circuits to perform the voltage window comparisons. Each comparator circuit includes a differential input stage made up of a pair of transistors and receiving a current source. A current mirror is coupled to the differential input state. Successive comparator circuits are coupled together via interconnected input lines.

REFERENCES:
patent: 4542370 (1985-09-01), Yamada et al.
patent: 5532627 (1996-07-01), Kearney et al.

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