Analog value memory circuit

Details Analog value memory circuit Analog value memory circuit

1997-02-28

2000-08-15

Nelms, David

Static information storage and retrieval

Analog storage systems

365149, 365240, G11C 2700

Patent

active

061046264

ABSTRACT:
An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1 Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.

REFERENCES:
patent: 3971055 (1976-07-01), Arai
patent: 4094007 (1978-06-01), Minami
patent: 4271488 (1981-06-01), Saxe
patent: 4536795 (1995-08-01), Hirota et al.
patent: 5206726 (1993-04-01), Okuda

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