Analog to digital converters with convergence accelerating signa

Details Analog to digital converters with convergence accelerating signa Analog to digital converters with convergence accelerating signa

1990-06-27

1991-11-19

Pellinen, A. D

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341166, H03M 150

Patent

active

050669559

ABSTRACT:
Integrating analog to digital converter operating according to a multiple ramp procedure and having a charge storage or charge summation circuit which continuously up-integrates an input signal and which by means of a following comparator, a logic circuit and reference currents or reference voltages, down-integrates during periodically recurrent time intervals, the instants being defined by an oscillator, a timebase counter and a bistable stage. The time between two successive such instants being called a submeasurement. At the imput of the charge storage or charge summation circuit used for the input signal or at one its other inputs, convergence accelerating signals are superimposed after every nth (n=1,2,3, . . . ) submeasurement to provide for strongly enhanced convergence range and for shorter convergence period, and these convergence accelerating signals having Taylor series expansions according to time in the time interval of a submeasurement which are first or higher order polynomials.

REFERENCES:
patent: 3765012 (1973-10-01), Grutzediek et al.
patent: 3942174 (1976-03-01), Dorey et al.
patent: 3943506 (1976-03-01), Peattie
patent: 4354245 (1982-10-01), Delegue
patent: 4361831 (1982-11-01), Grutzediek et al.
A. Klauer & M. Pandit, "Processing Measurement Signals with High Resolution AD-Conversion", Nov. 1985, vol. 11, pp. 404-410, Technisches Messen.

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