Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-08-02
2003-08-12
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C330S009000, C327S124000
Reexamination Certificate
active
06606049
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to systems and methods for obtaining digital representations of analog electrical signals. More specifically, the present invention relates to systems and methods for performing analog-to-digital conversion using transconveyance (charge-transfer) amplifiers.
2. Background and Relevant Art
There currently exists a strong demand for high-performance semiconductor circuits with reduced power dissipation. This demand is driven by a need for highly mobile and highly functional electronics in a variety of industries such as, for example, medicine, communications, military, and home. One particular type of circuit where this demand for reduced power dissipation exists is in analog-to-digital converters (“ADCs”). ADCs can significantly influence the cost of interfacing to real world signals including, sound, motion, vibration, light intensity, or electrical, and in some cases ADCs can account for up to half of the total power consumed by an integrated circuit. Consequently, power dissipation reduction techniques for ADCs, particularly those techniques that preserve high performance in terms of accuracy, speed, and size, are highly desirable.
There are many circuits and methods conventionally available for performing analog-to-digital conversion. Typically, an analog electrical signal (or a mechanical signal such as a vibration or sound) is sampled, digital values are generated from the samples, and multiple digital values are combined to provide a meaningful digital representation of the analog electrical signal.
Some common types of ADCs include flash converters, subranging converters, pipeline converters, flash-flash converters, delta sigma modulators, and successive approximation converters. Such ADCs often include some number of amplifiers, typically voltage-to-current amplifiers (also frequently referred to as transconductance amplifiers) or voltage-to-voltage amplifiers. The overall performance of these ADCs relies heavily on the properties of these amplifiers, since input and reference voltages feed directly to these amplifiers.
FIG. 1
illustrates a flash ADC
100
that utilizes multiple amplifiers during the analog-to-digital conversion process. The operation of the flash ADC
100
will now be described in order to illustrate the basic principles of analog-to-digital conversion.
Each amplifier in preamplifiers
102
receives two input signals, the analog input
105
and a reference voltage (e.g., one of reference voltages
101
). The reference voltages
101
vary incrementally. Preamplifiers
102
generate amplified output signals by amplifying the difference in the analog input and a corresponding reference voltage. Decision circuits
103
receive the amplified output signals and convert the amplified output signals to voltages representing a digital value of a logical “1” or “0.” Encoding logic
104
receives the representative digital values and maps the digital values into a meaningful digital representation of the analog input. As shown in
FIG. 1
, there is at least one amplifier for each digital value generated by flash analog-to-digital converter
100
.
Flash ADCs are often desirable because conversion from an analog signal to a digital representation is performed in a single step, or a “flash.” However, the resolution (the number of digital output bits generated) of flash converters, such as flash ADC
100
is constrained by the number of amplifiers that are configured to amplify the difference of an analog signal and a reference voltage. That is, flash ADC
100
can only resolve an analog signal to N or less bits if 2
N
−1 amplifiers are configured. For example, to achieve 8 bits of resolution 2
8
−1=255 amplifiers would be required. Therefore, a flash ADC can quickly become impossible to realize as 2
N
−1 amplifiers present a large area requirement and consume a very large amount of power. In many environments, it is desirable to achieve higher levels of resolution than those feasible with a single flash ADC. Other types of ADCs, such as the subranging ADC, overcome some of the constraints of flash ADCs.
Subranging ADCs essentially combine the functionality of two or more flash ADCs to increase output resolution. In an N-bit subranging ADC having two flash ADCs, a first flash ADC would convert an analog signal into m coarse bits. Subsequently, through electrical subranging (i.e., refining the value of the reference voltages), a second flash ADC would convert the analog signal into n fine bits, where m+n equals N, the total resolution. Thus, if the individual flash ADCs each had a resolution of 4 bits, a subranging ADC with two of the flash converters could produce a digital representation with 8 bits of resolution. Yet, the subranging amplifier would require only (2
4
−1)+(2
4
−1)=30 amplifiers.
FIG. 2
illustrates a subranging ADC
200
that utilizes two flash ADCs during the analog-to-digital conversion process. The operation of the subranging ADC
200
will now be described in order to illustrate a conventional subranging ADC technique.
Each amplifier included in coarse flash converter
201
receives the analog input and a coarse reference voltage from reference ladder
202
. Reference ladder
202
divides a range of voltages between a minimum and maximum voltage, for example, a range from zero volts to 5 volts, into multiple incrementally increasing coarse reference voltages. For example, using a 0.2 volt increment results in coarse reference values of 0.2 volts, 0.4 volts, 0.6 volts, and so forth. Coarse flash converter
201
uses the analog input and the coarse reference voltages to convert the analog signal into a number of coarse digital values. The coarse digital values are stored in the hold circuit
206
until fine flash converter
204
generates the fine digital bits in a manner that is now to be described.
Reference ladder
202
also divides the range of voltages into multiple incrementally increasing fine reference voltages that more closely approximate the actual value of the analog input signal. This closer approximation is generated using the coarse digital bits as an input and thus the increment for fine reference values is decreased when compared to that used for coarse reference values. However, the fine reference voltages take some amount of time to approach or “settle to” their final values since generation of the fine reference voltages is delayed by at least the amount of time taken to generate the coarse digital bits. As such, the analog input must be held at fine flash converter
204
while these fine reference voltages settle. In
FIG. 2
, analog sample and hold circuit
207
performs this hold function. Typically, sample and hold circuit
207
is a global sample and hold circuit that may be accessed by any of the components included in subranging ADC
200
. The circuitry required to implement a sample and hold circuit consumes space, increasing the overall size of subranging ADC
200
, and consumes power, increasing the overall power dissipation of subranging ADC
200
.
After the fine reference voltages settle, fine reference multiplexer
203
receives the fine reference voltages and the coarse digital values. The coarse digital values are then used to select which of the fine reference voltages best approximate the analog signal at the sampling time. Fine reference multiplexer
203
then outputs those selected fine reference voltages to the fine flash converter
204
.
Each amplifier of fine flash converter
204
receives the analog input, which was being held in analog sample and hold circuit
207
, and a subranged fine reference voltage. Fine flash converter
204
uses the analog input and the subranged fine reference voltages to convert the analog signal into a number of fine digital values. Encoding logic
205
combines the coarse digital values and fine digital values into a meaningful digital representation of the analog input.
Subranging ADCs are advantageous due to the increased output res
AMI Semiconductor Inc.
Jeanpierre Peguy
Workman & Nydegger & Seeley
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