Analog-to-digital converter without track-and-hold

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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C341S122000, C341S155000

Reexamination Certificate

active

07339512

ABSTRACT:
A system and method for converting an analog signal to a digital signal is provided. The analog to digital conversion is achieved without a dedicated sample-and-hold circuit. An ADC stage, preferably the front-end stage in the case of a pipeline ADC, samples the input voltage within a quantizer and within a residue generator. The sampling is performed with associated clocking signals and with switch capacitors also fulfilling the comparison with threshold voltages, within the quantizer and the generation of a residue signal within the residue generator.

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Mehr and Singer, “A 55-mW, 10-bit 40-Msample/s Nyquist-Rate CMOS ADC,”IEEE J. of Solid-State Circuits, 35(3) Mar. 2000.
Chiu, et al., “A 1.8V 14b 10MS/s Pipelined ADC in 0.18um CMOS with 99dB SFDR,”International Solid-State Circuits Conference, Feb. 2004.
Sumanen L., “Pipeline Analog-to Digital Converters for Wide-Band Wireless Communications”, PhD Thesis, Dept. of Electrical and Comm. Eng. Of Helsinki University of Technology, Dec. 13, 2002.

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