Analog-to-digital converter with the ability to...

Details Analog-to-digital converter with the ability to... Analog-to-digital converter with the ability to...

2002-05-02

2003-12-23

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S150000, C341S155000, C341S163000

Reexamination Certificate

active

06667707

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of analog-to-digital converters and, more particularly, to a charge redistribution analog-to-digital converter that provides for asynchronously sampling signals in a fully powered-down state of the converter.
BACKGROUND
Analog-to-digital converters (ADCs) are well-known and are in widespread use. With the recent high growth of portable electronics systems, the requirement for long lasting low power battery operated systems has become paramount. ADCs are often required to take samples of randomly occurring events and thus must be able to idle for extended periods of time until these events occur. During that time, power is dissipated as the ADC system awaits in readiness to acquire these events. Generally, this “stand-by” power is associated with a reference or bias voltage either internal or external to the ADC. In order to extend battery life, many systems will essentially completely power down and awake when the random event occurs in order to be able to sample the event. This awakening process takes time and, thus, the actual capability to capture the event's beginnings is curtailed.
There exists a need for an essentially completely powered down ADC system which can respond instantly to a sampling request.
One type of ADC is a so-called “switched-capacitor,” or charge redistribution, converter in which an input voltage is sampled as charge across an array of capacitors during a first time phase. Thereafter, charge is redistributed as the converter determines a digital “equivalent” to the sampled input voltage. One well-known ADC that makes use of switched capacitor circuitry is the so-called successive approximation routine (SAR) converter.
A differential input, charge redistribution SAR ADC is shown in FIG.
1
. It samples a pair of input voltages, Vinp and Vinn, with respect to a datum, or common-mode bias voltage, Vcm, and, under the control of a successive approximation routine (SAR) engine, produces a sequence of binary decisions at the output, OUT, which correspond to the digital equivalent of the input voltage difference with respect to the reference voltage difference, (Vrefp−Vrefn).
The ADC system
100
shown comprises two digital-to-analog converters (DACs), DAC-P and DAC-N, a comparator
12
, and an SAR engine (not shown) to drive the DACs. Each DAC comprises (for this example) a 6-bit binary-weighted capacitor array
14
P,
14
N, where the total capacitance of each array
14
P,
14
N is C. The DACs further comprise two corresponding sets
16
P,
16
N of switches to connect the respective DAC inputs to Vinp
, and corresponding sets
18
P,
18
N of switches to connect the respective DAC inputs to Vrefp
, as well as switches
20
P,
20
N to connect the DAC outputs, TOP-P, TOP-N, to the datum or common-mode voltage point(s), Vcm.
In the example shown in
FIG. 1
, each of the weighted capacitor arrays
14
N (associated with DAC-N) and
14
P (associated with DAC-P) includes capacitors C
1
, C
2
, C
3
, C
4
, C
5
, C
6
and C
7
. The capacitances of such capacitors, with respect to the total capacitance C of the array, is as follows: C
1
=C/2, C
2
=C/4, C
3
=C/8, C
4
=C/16, C
5
=C/32, C
6
=C/64 and C
7
=C/64. The sum of the capacitances of C
1
-C
7
equals C.
Each of switch sets
16
N (associated with DAC-N) and
16
P (associated with DAC-P) includes switches S
1
, S
2
, S
3
, S
4
, S
5
and S
6
. Each of switch sets
18
N (associated with DAC-N) and
18
P (associated with DAC-P) includes switches S
21
, S
22
, S
23
, S
24
, S
25
and S
26
.
The DAC outputs TOP-P, TOP-N, provide input voltages to the comparator
12
. The plates of the capacitors directly connected to the outputs TOP-P, TOP-N are referred to as the “top plates” with the other capacitor plates referred to as the “bottom plates.” The switches to Vcm are referred to as the “top-plate switches”
20
P,
20
N.
During operation, an input voltage is sampled as charge across the input capacitors. With the DAC bottom plates connected to the input voltage Vinp and Vinn through switches
16
P and
16
N, when the top-plate switches
20
P and
20
N are closed, the DAC is said to be “sampling the input”, and the instant at which the top plate switches open, the DAC is said to have “taken the sample”.
After sampling the input voltage, the SAR ADC
100
carries out an iterative process, referred to as a successive approximation routine (SAR). Using the P-side of the circuit as an example, the SAR iterative process begins by connecting the bottom plate of each of the capacitor array
14
P capacitors C
1
. . . C
6
, through its corresponding switch S
1
. . . S
6
in switch bank
16
P and a corresponding switch S
21
. . . S
26
in switch bank
18
P, to either the positive reference voltage Vrefp or the negative reference voltage Vrefn. Each capacitor, e.g. C
4
, represents one of the bits in the digital output word of the ADC
100
, the most significant (MSB) of which corresponds to capacitor C
1
and the least significant bit (LSB) of which corresponds to capacitor C
6
.
In an exemplary embodiment, a bit has a binary value of 1 when the bottom plate of the associated capacitor, e.g. C
4
, is connected to the positive reference voltage Vrefp and the bit has a binary value of 0 when the bottom plate of the capacitor, e.g. C
4
, is connected to the negative reference voltage Vrefn through switch bank
18
. In this example, switch S
4
would get switched to connect capacitor C
4
to the Vref set (not the Vinp position) and switch S
24
would get aligned to connect capacitor C
4
to either Vrefp or Vrefn, depending on whether C
4
was to represent a logical 1 or 0, respectively.
As those skilled in the art will appreciate, through such a series of SAR iterations, starting with the MSB capacitor and ending with the LSB capacitor, wherein, during each iteration, each capacitor is switched to either Vrefp or Vrefn such that the top plate voltages, TOP-P and TOP-N, converge with each iteration. When the iterations have completed, the last-used digital word (the value of the bits to which the capacitors were connected) is selected as the output of the ADC. These iterations are graphically depicted later.
For pseudo-differential operation, Vinn (often referred to as a “ground sense”) is held at a voltage near Vrefn. The ADC
100
is powered by voltage supplies of VDD (positive) and VSS (negative) and the reference voltage inputs are Vrefp and Vrefn. The DAC top plates are sampled to Vcm, which is an arbitrary but constant voltage typically mid-way between VDD and VSS. Note that during sampling, TOP-P and TOP-N will be nominally held at approximately Vcm by the top plate switches.
FIGS. 2A-C
show an aspect of the pseudo-differential operation of the DAC
100
of FIG.
1
.
FIGS. 2A-C
, and all subsequent similar figures, depict the top plate voltages TOP-P, TOP-N after the sample is taken and the digital words shown are presented to the SAR-P and SAR-N switches. SAR-N=000000 in
FIGS. 2A-C
, and SAR-P values are shown along the horizontal axis for each of a number of iterations in the SAR process.
As an example,
FIG. 2A
shows the output voltage
202
A of TOP-P, as well as voltage
204
A for TOP-N with Vinp=Vrefn. The voltage
202
A decreases monotonically, and the bit sequence at SAR-P is shown along the horizontal axis, and is 100000 at the first iteration and 010000, 001000, 000100, 000010, 000001 at subsequent successive iterations of the SAR.
FIG. 2B
shows an analogous situation for voltages
202
B below Vcm with Vinp=Vrefp. The TOP-P voltage
202
B is monotonically increasing. The SAR-P bit sequence changes from initial value 100000 to 110000, 111000, 111100, 111110, 111111 on subsequent successive iterations of the SAR.
FIG. 2C
shows the situation for Vinp=⅜*Vrefp. The TOP-P voltage
202
C here is not monotonic, and the SAR-P sequence is 100000, 010000, 011000, 010100, 010110, 010111.
The reader should note that, during the course of the SAR, several thing

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