Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices
Patent
1994-10-05
1997-02-11
Williams, Howard L.
Coded data generation or conversion
Analog to or from digital conversion
With particular solid state devices
341158, 341159, 257318, H03M 136, H01L 2176, H01L 2968
Patent
active
056025513
ABSTRACT:
A converter is provided having a layout which can be easily designed and which requires a small chip area. Four MOS transistors having the same layout are disposed on the same substrate, and a polycrystalline silicon layer extends under the MOS transistors in the substrate. A predetermined voltage is applied to the polycrystalline silicon layer. This applied voltage continuously controls threshold voltages of the MOS transistors. An analog signal is input to gate terminals of the MOS transistors and is digitized in accordance with on and off states of the MOS transistors.
REFERENCES:
patent: 4872010 (1989-10-01), Larson et al.
patent: 5134456 (1992-07-01), Kobatake
Shibata et al. An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum And Threshold Operations, IEEE International Electron Devices Meeting, Dec. 8-11, 1991, vol. IEDM 91, pp. 919-922.
Silburt et al. A Novel Multiple Threshold MOSFET Structure for A/D and D/A Conversion, IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5 pp. 794-802, Oct. 1984.
Fukumoto Harutsugu
Ichikawa Kohji
Nippondenso Co. Ltd.
Williams Howard L.
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