Analog-to-digital converter with pulse delay circuit

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C341S155000, C341S166000

Reexamination Certificate

active

07423574

ABSTRACT:
In a semiconductor-integrated A/D converter, a pulse delay circuit is provided with a plurality of delay units. The plurality of delay units each includes at least one logic gate and operates based on a level of an input signal. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on the level of the input signal. The at least one logic gate is composed of at least one first transistor. The at least one first transistor has a first threshold voltage. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate digital data based on the obtained number. The generating circuit is composed of at least one second transistor. The at least one second transistor has a second threshold voltage. The first threshold voltage of the at least one first transistor is lower than the second threshold voltage of the at least one second transistor.

REFERENCES:
patent: 5396247 (1995-03-01), Watanabe et al.
patent: 6466151 (2002-10-01), Nishii et al.
patent: 6509861 (2003-01-01), Watanabe
patent: 6771202 (2004-08-01), Watanabe et al.
patent: 6940443 (2005-09-01), Terazawa et al.
patent: 7030803 (2006-04-01), Harada et al.
patent: 5-259907 (1993-10-01), None
patent: 2005-94341 (2005-04-01), None
patent: 2005-229263 (2005-08-01), None

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