Analog-to-digital converter with offset voltage polarity inversi

Details Analog-to-digital converter with offset voltage polarity inversi Analog-to-digital converter with offset voltage polarity inversi

1988-12-02

1990-03-06

Shoop, Jr., William M.

Coded data generation or conversion

Converter compensation

341129, 341167, 341168, 324 99D, H03M 106

Patent

active

049069969

ABSTRACT:
There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal. During deintegration of the capacitor by a reference signal the polarity of the error signal is inverted during successive or consecutive deintegration cycles so that the error voltage is self-cancelling in two successive deintegrations and is eliminated from the summed digital output.

REFERENCES:
patent: 4195283 (1980-03-01), Ishikawa
patent: 4243975 (1981-01-01), Masuda et al.
patent: 4309692 (1982-01-01), Crosby
patent: 4315253 (1982-02-01), Tytus
patent: 4556867 (1985-12-01), George
patent: 4633233 (1986-12-01), Senderowicz
patent: 4764752 (1988-08-01), Ormond
patent: 4764753 (1988-08-01), Yukawa

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