Analog to digital converter with integral linearity error compen

Details Analog to digital converter with integral linearity error compen Analog to digital converter with integral linearity error compen

1988-01-28

1990-05-08

Shoop, Jr., William M.

Coded data generation or conversion

Converter compensation

341155, H03M 106

Patent

active

049242253

ABSTRACT:
Integral linearity error in the operating characteristics of an analog to digital converter employing sampling comparators is reduced by recurrently connecting at least one resistive shunt across a predetermined central portion of a reference voltage divider input to the comparators. The shunt resistance is approximately an order of magnitude larger than the resistance of the shunted part of the divider. Each recurrent connection interval is of fixed duration independent of sampling rate, and each interval spans the beginning of a recurrent time of connection of said divider to said comparators.

REFERENCES:
patent: 3710377 (1973-01-01), Guillen et al.
patent: 4496935 (1985-01-01), Inoue et al.
patent: 4650347 (1987-03-01), Shigemura et al.

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