Analog-to-digital converter with flush access to...

Details Analog-to-digital converter with flush access to... Analog-to-digital converter with flush access to...

1999-07-30

2001-06-12

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S163000, C341S154000

Reexamination Certificate

active

06246352

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to data converters, and are more particularly directed to an analog-to-digital converter based in part upon a digital-to-analog converter.
Data converters may be used in various types of electronic circuits, or may be formed as a single integrated circuit device. Such converters typically take one of two forms, either as a digital-to-analog converter (“DAC”) or an analog-to-digital converter (“ADC”). For the DAC, its operation converts an input digital signal to an output analog signal, typically where the amplitude of the output analog signal corresponds directly to the magnitude of the input digital signal. Conversely, the ADC converts an input analog signal to an output digital signal, typically where the value of the output digital signal corresponds directly to the amplitude of the input analog signal. In many configurations, both DACs and ADCs implement a resistor string that includes a number of series-connected resistors, where each resistor provides a voltage tap at each of its ends. Typically, the overall string is biased at opposing ends by two different reference voltages, where for example one such voltage is a positive voltage and the other is ground. Also in this regard, in an effort to maintain the linearity between the digital input and the analog output, a common concern in the art is to endeavor to ensure that each resistor in the string has as close to the same resistance value as all other resistors in the string. Accordingly, the resistor string forms a series voltage dividing network and each of the voltage taps is accessible as part of the operation for the data conversion (i.e., either from digital to analog, or analog to digital).
For further background to converters, it is noted that often ADCs are formed using one or more stages that include a DAC for each stage. Accordingly, by way of further introduction and example,
FIG. 1
illustrates a typical configuration of a prior art DAC
10
, and is detailed briefly below. Once an understanding for such a DAC is presented, additional aspects are treated whereby such a DAC is used in the prior art to form an ADC.
FIG. 1
illustrates a typical configuration of a prior art DAC
10
, and is detailed briefly here with additional detail ascertainable by one skilled in the art. By way of example and as appreciated later, DAC
10
is a 4-input 16-output DAC, while numerous other dimensions may exist for different DAC configurations. In general and as detailed below, DAC
10
is operable to receive a 4-bit input word, designated from least significant bit to most significant bit as I
0
-I
3
. In response to the magnitude of these bits, DAC
10
outputs a corresponding analog voltage. Before detailing this operation, it is first instructive to examine the devices and connections of DAC
10
. In this regard, DAC
10
includes a series-connected resistor string designated generally at
12
, and that forms a meander in that it serpentines back and forth. Additionally, DAC
10
is generally a symmetric array in nature, having a number of bit lines in the vertical dimension and a number of word lines in the horizontal dimension. Since the example of DAC
10
presents a 4input 16-output DAC, the array of DAC
10
includes four bit lines BL
0
through BL
3
, and four word lines WL
0
through WL
3
. Also for the current example of a 4-to-16 DAC, resistor string
12
includes fifteen resistive elements R
0
through R
14
. Resistive elements R
0
through R
14
may be formed using various techniques, where regardless of the technique ideally each resistive element has as close to the same resistance value as all other resistors in the string. Moreover, a voltage source V
REF1
is applied across resistor string
12
, and may be of any suitable biasing voltage, which for current applications is typically on the order of 2.0 volts. For DAC
10
, string
12
is biased between V
REF1
and ground, but it should be understood that in other configurations two different non-ground potentials may be connected at opposing ends of string
12
. When ground is connected to one end of the string, it is easily appreciated that this difference of the potentials at the ends of the string equals V
REF1
. In any event, given the equal resistance of each element in the string, V
REF1
is uniformly divided across the resistive elements of string
12
.
Looking to the detailed connections with respect to resistive elements R
0
through R
14
, each resistive element provides two taps and, therefore, two voltages that may be sampled as detailed below. For example, looking to resistive element R
0
, it provides a tap T
0
and a tap T
1
, while resistive element R
1
shares the same tap T
1
and provides another tap T
2
, and so forth. Each tap has a switching device connected between it and a corresponding output bit line. In the current example, each of these switching devices is an n-channel field effect transistor, and is labeled for convenience by combining the abbreviation ST (i.e., switching transistor) with the same numeric identifier corresponding to the tap to which a source/drain of the transistor is connected. For example, a source/drain of transistor ST
0
is connected to tap T
0
, a source/drain of transistor ST
1
is connected to tap T
1
, and so forth. Further, the switching transistors are arranged so that a like number of taps are coupled via corresponding switching transistors to a corresponding one of the bit lines. In the current example of DAC
10
, four taps are coupled in this manner to a corresponding bit line. For example, taps T
0
through T
3
are coupled, via corresponding switching transistors ST
0
through ST
3
, to bit line BL
0
. As another example, taps T
4
through T
7
are coupled, via corresponding switching transistors ST
4
through ST
7
, to bit line BL
1
. Each bit line BL
0
through BL
3
is coupled to a first source/drain of a respective column access transistor, CAT
0
through CAT
3
, where the second source/drains of the column access transistors are connected to the output V
OUT1
. In addition, column decoder
14
is coupled to receive the two most significant bits (MSBs) of the 4-bit word input to DAC
10
, and in response column decoder
14
controls the gates of column access transistors CAT
0
through CAT
3
.
Returning now to switching transistors ST
0
through ST
15
, and given the array nature of DAC
10
, it is further appreciated that the switching transistors are arranged so that a like number of switching transistors are controlled, via connection to their gates, by a corresponding word line that is further connected to row decoder
16
. Given the current example of DAC
10
, the gates of four switching transistors are coupled to each corresponding word line. For example, the gates of switching transistors ST
0
, ST
7
, ST
8
, and ST
15
are coupled to word line WL
0
. As another example, the gates of switching transistors ST
1
, ST
6
, ST
9
, and ST
14
are coupled to word line WL
1
. Lastly in this regard, and for reasons evident below, row decoder
16
is coupled to receive the two least significant bits (LSBs) of the 4-bit word input to DAC
10
(i.e., bits I
1
and I
0
), and is also controlled in response to the least significant bit (“Isb”), I
2
, of the two MSBs input to column decoder
14
. More particularly, each least significant bit I
0
and I
1
is coupled as an input to a corresponding exclusive OR gate EOG
0
and EOG
1
as a first input, while the second input of exclusive OR gates EOG
0
and EOG
1
is connected to receive
12
(i.e., the least significant bit of the two MSBs input to column decoder
14
). In response to these bits, row decoder
16
controls the gates of switching transistors ST
0
through ST
15
as detailed below.
The operation of DAC
10
is now described, first in general and then more specifically through the use of a few examples. A 4-bit digital word is connected to i

Affiliated with

Also associated with

Rating

Analog-to-digital converter with flush access to... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Analog-to-digital converter with flush access to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Analog-to-digital converter with flush access to... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2524132