Analog to digital converter with encoder circuit and testing...

Details Analog to digital converter with encoder circuit and testing... Analog to digital converter with encoder circuit and testing...

2001-07-18

2004-03-09

Young, Brian (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S097000

Reexamination Certificate

active

06703951

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an analog to digital (A/D) converter, and, more particularly, to an A/D converter including an encoder.
A/D converters are often used with microprocessors to convert an analog signal to a corresponding digital signal which is processed by the microprocessor. Due to the increased speed of microprocessors, for example, from 50 MHZ to 300 MHZ, there is a need for faster A/D converters. A/D converters of the parallel type and the serial and parallel type are advantageous for high speed operation. Such A/D converters generally comprise a plurality of comparators for comparing an analog input signal with analog reference voltages and an encoder for converting output signals of the comparators to a multibit digital signal. The speed and accuracy of the A/D converter can be improved by increasing the speed and accuracy of the encoder.
A conventional, parallel-type A/D converter comprises a comparator section, a logical boundary detection section for detecting a logical boundary of comparator output signals and an encoder section. The encoder section often includes a wired-OR type ROM. Referring to
FIG. 1
, a first example of a conventional parallel-type A/D converter which outputs a five (5) bit digital signal is shown. The A/D converter comprises a comparator section
1
having comparators CM
1
to CM
31
and associated resistors R, a logical boundary detection section
2
having NOR circuits DE
0
to DE
31
, and an encoder section
3
a
having ROM cells
4
.
Between a high potential side reference voltage V
RH
and a low potential side reference voltage V
RL
, thirty two resistors are connected in series. The two resistors R positioned on opposite ends of the series connection have a resistance value equal to half that of the other resistors R. A junction between each adjacent one of the resistors R is connected to a first input terminal of a corresponding one of 31 comparators CM
1
to CM
31
. A voltage difference between the reference voltages V
RH
and V
RL
is divided by the resistors R, and reference voltages V
R1
to V
R31
obtained by the division are input to the comparators CM
1
to CM
31
, respectively. An analog input signal Ain is input to second terminals of the comparators CM
1
to CM
31
. The comparators CM
1
to CM
31
compare the analog input signal Ain with the reference voltages V
R1
to VR
31
, in response to a control signal output from a control circuit (not shown).
Each of the comparators CM
1
to CM
31
outputs an output signal S
1
to S
31
high and an output signal /S
1
to /S
31
low when the potential of the analog input signal Ain is lower than the reference voltage V
R1
to V
R31
. On the other hand, when the potential of the analog input signal Ain is higher than the reference voltage V
R1
to V
R31
, each of the comparators CM
1
to CM
31
outputs an output signal S
1
to S
31
low and an output signal /S
1
to /S
31
high.
For example, if the potential of the analog input signal Ain is higher than the reference voltage V
R4
but lower than the reference voltage V
R5
, then the comparators CM
1
to CM
4
output thermometer code bits wherein the output signals S
1
to S
4
have L levels and the output signals /S
1
to /S
4
have H levels. Meanwhile, the comparators CM
5
to CM
31
output thermometer code bits wherein the output signals S
5
to S
31
have H levels and the output signals /S
5
to /S
31
have L levels.
Each of the output signals S
1
to S
31
of the comparators CM
1
to CM
31
is input to a first terminal of a corresponding one of the NOR circuits DE
1
to DE
31
while each of the output signals /S
1
to /S
31
of the comparators CM
1
to CM
31
is input to a second input terminal of a corresponding one of the NOR circuits DE
0
to DE
30
. Further, one of a pair of terminals of each of the NOR circuits DE
0
and DE
31
is connected to the ground GND. Each of the NOR circuits DE
0
to DE
31
outputs a signal high if both of the input signals thereto have L levels, and only one of the NOR circuits DE
0
to DE
31
outputs a signal high by operation of the comparators CM
1
to CM
31
. The output signals of the NOR circuits DE
0
to DE
31
are output to word lines WL
0
to WL
31
, respectively.
The encoder section
3
a
includes five bit lines BL
0
to BL
4
corresponding to a 5-bit digital output signal B
0
to B
4
. ROM cells
4
for outputting the output signal B
0
to B
4
in the form of a binary code are connected at predetermined locations between the word lines WL
0
to WL
31
and the bit lines BL
0
to BL
4
. Each of the ROM cells
4
comprises an N-channel MOS transistor, shown in FIG.
2
. The gate of the transistor is connected to one of the word lines WL and the drain is connected to one of the bit lines BL while the source is connected to the ground GND.
The bit lines BL
0
to BL
4
are connected to a power supply V
DD
through switch circuits SW
0
to SW
4
, respectively, such that, when the switch circuits SW
0
to SW
4
are closed, the bit lines BL
0
to BL
4
are precharged. Each of the switch circuits SW
0
to SW
4
preferably comprises a P-channel MOS transistor.
If the level of one of the word lines changes to an H level after the switch circuits SW
0
to SW
4
are opened, then ROM cells connected to the activated word line are turned on and the levels of the bit lines which are connected to the ROM cells are changed to an L level. For example, if the level of the word line WL
0
is changed to an H level, then the output signals B
0
to B
4
are “00000”; and if the level of the word line WL
2
is changed to an H level, then the output signals B
0
to B
4
are “01000”.
Since the encoder section
3
a
employs a ROM circuit which requires a precharging operation, the operation speed of the comparator section
1
is lower than the operation speed of the encoder section
3
a
. Accordingly, the conversion speed is determined by the comparator section
1
.
The output signals of the comparator section
1
in normal operation either are a thermometer code which exhibits only one logical boundary or exhibit the same logic value. However, a babble error sometimes occurs with a thermometer code. The babble error which occurs probabilistically most frequently is reversal of one output logic value in the output signals /S
1
to /S
31
of the comparators CM
1
to CM
31
. If such a babble error is input to the NOR circuits DE
0
to DE
31
, then two word lines exhibit H levels simultaneously, and an incorrect output signal B
0
to B
4
is output.
Particularly, the encoder section
3
a
constructed to output a binary code, sometimes has a large error due to a babble error. In particular, if the word lines WL
14
and WL
16
shown in
FIG. 3
exhibit H levels simultaneously due to a babble error, then the output signal B
0
to B
4
are all zero and a large error occurs with the output signal B
0
to B
4
.
In order to solve such a problem, an A/D converter having a modified logical boundary detection section
2
, as shown in
FIG. 4
, has been proposed. Referring to
FIG. 4
, the A/D converter is constructed such that the NOR circuits DE
0
to DE
31
have 3-input terminals. If an nth NOR circuit is represented as NOR circuit DEn, an output signal Sn of the comparators CMn and output signals /S(n+1) and /S(n+2) of two higher order comparators CM(n+1) and CM(n+2) are input to the NOR circuit DEn. When a babble error (a different logic value is included in a thermometer code) occurs, the babble error location is not discriminated as a logical boundary, and only one of the word lines WL exhibits H levels and an output signals B
0
to B
4
having correct values or values near to correct values are output.
However, even where the NOR circuits DE
0
to DE
31
have 3-inputs, if, for example, such a babble error that an output logic value spaced by a two or more logic value distance is reversed, then two word lines spaced by a two word line distance exhibit an H level simultaneously. If, for example, the word lines WL
14
and WL
17
shown in
FIG. 3
simultaneously exhibi

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