Analog to digital converter with continuous conversion cycles an

Details Analog to digital converter with continuous conversion cycles an Analog to digital converter with continuous conversion cycles an

1994-12-30

1996-10-01

Gaffin, Jeffrey A.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341139, H03M 138, H03M 118

Patent

active

055614272

ABSTRACT:
A successive approximation A/D having dual comparators for allowing a larger range of analog input signals to be converted into digital form. One comparator is an N-channel device, and the other comparator is a P-channel device. The A/D switches to either the N-channel device or the P-channel device based upon whether the first two comparisons determine the most-significant bit and the next-most significant bit are a "11", in which the N-channel device is selected, or anything else, in which the P-channel device is selected. Switching circuitry is included to output the proper comparator based on these two comparisons.
Control circuitry is also provided to allow for successive conversions using only a single address read. A one-half clock cycle reset occurs at the start of every MSB comparison for every n-bit read, and this reset goes to every component in the A/D except the latch for the LSB, which must be held for at least one more clock cycle before since it has not yet been output to the data bus as yet. Gate circuitry is also added to the input of the D/A portion of the A/D, in which the LSB is not allowed to be input to the D/A until after the MSB comparison has been performed for the next n-bit read.

REFERENCES:
patent: 4593270 (1986-06-01), White
patent: 4771266 (1988-09-01), Nunokawa
patent: 4777470 (1988-10-01), Naylor et al.
patent: 4940981 (1990-07-01), Naylor et al.
patent: 4989004 (1991-01-01), Kanayama
patent: 4999628 (1991-03-01), Kakubo et al.
patent: 5377248 (1994-12-01), Brooks

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