Analog-to-digital converter with cascaded switching control of v

Details Analog-to-digital converter with cascaded switching control of v Analog-to-digital converter with cascaded switching control of v

1993-06-03

1996-10-08

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341159, H03M 114

Patent

active

055635997

ABSTRACT:
The invention concerns an analog to digital converter (ADC1, ADC2) for converting an analog input voltage (Vin) into a digital output voltage (Dout) in at least two stages, (B1, B2, B3, B1', B2', B3'). The reference voltage (Vref) or part thereof driving a stage is applied to that stage via switching means so that the voltage applied to the latter means is determined when the switching means is set, i.e. the latter voltage is not dependent of the setting of the switching means. Two implementations of the converter are described, one (ADC1) which produces the digital signal (Dout) before another analog voltage (Vin) can be processed, and another (ADC2) which allows another analog voltage (Vin) to be processed by a stage after the output of that stage is produced.

REFERENCES:
patent: 4008468 (1977-02-01), Imhoff et al.
patent: 4542370 (1985-09-01), Yamada et al.
patent: 4571574 (1986-02-01), Krynicki
patent: 4602241 (1986-07-01), Dingwall
patent: 4749984 (1988-06-01), Prost et al.
patent: 5066954 (1991-05-01), Burgel et al.
patent: 5327135 (1994-07-01), Hosotani et al.
"Session 1: Data Converters--WAM 1.2: a CMOS 40 MHz 8b 105 mW Two-Step ADC", M. Ishikawa et al, Proceedings of the IEEE International Solid-State Circuits Conference, Feb. 15, 1989, pp. 14-18.
"Session 1: Data Converters--WAM 1.2: A CMOS 40MHz 8b 105mW Two-Step ADC", N. Fukushima et al, Proceedings of the IEEE International Solid-State Circuits Conference, Feb. 15, 1989, New York, pp. 14-15.

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