Analog-to-digital converter with a power saving capability

Details Analog-to-digital converter with a power saving capability Analog-to-digital converter with a power saving capability

2000-03-21

2002-11-12

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06480134

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog-to-digital (AD) converter for converting an analog voltage to digital data and more particularly to an improvement in the conversion accuracy of a parallel comparison type AD converter.
2. Description of the Background Art
To better understand the present invention, reference will be made to a conventional parallel comparison type AD converter, shown in FIG.
1
. As shown, the AD converter is constructed to compare an analog voltage AI input thereto with n different reference voltages VR
1
, VR
2
, . . . , VRn at the same time and output binary digital data DO on the basis of the results of comparison, where n is a positive integer. The AD converter includes a voltage dividing circuit for producing the reference voltages VRi (i is a positive integer not exceeding n) and n CMOS (Complementary Metal Oxide Semiconductor) chopper type comparators
10
1
,
10
2
, . . . ,
10
n
.
The voltage dividing circuit has n+
1
resistors
1
1
,
1
2
, . . . ,
1
n+1
serially connected between a low reference potential VRB and a high reference potential VRT. The reference voltages VRi each appear at a junction between two adjoining resistors
1
1
and
1
i+1
.
The comparators
10
1
through
10
n
are identical in configuration with each other. The comparator
10
1
, for example, includes analog switches
11
and
12
to which the reference voltage VR
1
and analog voltage AI, respectively, are input. The switches
11
and
12
have outputs connected to a node N
1
. A capacitor
13
is connected to the node N
1
at one end and connected to the input of an inverter
14
at the other end. The inverter
14
is implemented by a CMOS. A signal S
1
representative of the result of comparison appears on the output of the inverter
14
. The other comparators
10
2
through
10
n
also output respective signals S
2
through Sn representative of the results of comparison.
An analog switch
15
is connected in parallel to the inverter
14
. The switches
11
,
12
and
15
are semiconductor switches implemented by, e.g., MOS transistors. The switches
11
,
12
and
15
each turn on when a control signal is in its high level or turn off when it is in its low level. Specifically, a controller
2
feeds a clock signal CK
1
to the switches
12
and
15
as a control signal and feeds the clock signal CK
1
to the switch
11
via an inverter
16
.
The comparators
10
1
through
10
n
have outputs connected to the input side of a data latch
3
. The controller
2
feeds a clock signal CK
2
to the data latch
3
. The data latch
3
latches and then outputs the signals S
1
through Sn output from the comparators
10
1
through
10
n
at the same time in response to the clock signal CK
2
.
An error correcting circuit
4
is connected to the output side of the data latch
3
for correcting the results of comparison output from the comparators
10
1
through
10
n
if they are illogical. The error correcting circuit
4
includes biinput AND gates
4
2
, . . . ,
4
n
each receiving the result of comparison from the lower AND gate preceding it. and delivering its output to the higher AND gate following it.
An encoder
5
is connected to the output side of the error correcting circuit
4
. The encoder
5
codes corrected signals CS
1
through CSn output from the error correcting circuit
4
to generate the previously mentioned binary digital data DO.
In operation, when the clock signal CK
1
output from the controller
2
is in its high level, the switches
1
2
and
1
1
of each comparator
10
1
are turned on and turned off, respectively. As a result, the analog voltage AI appears on the node N
1
. Further, the switch
15
is turned on to short-circuit the input and output of the inverter
14
with the result that the input and output voltages of the inverter
14
become equal to a threshold voltage VT which is substantially one half of a power source voltage VDD. Consequently, the capacitor
13
is charged to a voltage VT−AI.
When the clock signal CK
1
goes low, the switch
15
of each comparator
10
i
is turned off to cause the inverter
14
to operate as an inverting amplifier. At the same time, the switches
11
and
12
are turned on and turned off, respectively, so that the reference voltage VRi is applied to the node N
1
. Because the capacitor
13
has already been charged to the voltage VT−AI, a voltage VT−AI+VRi is input to the inverter
14
. Consequently, the signal Si output from the inverter
14
of the comparator
10
i
is in its high level when the voltage Al is higher than the voltage VRi (Al>VRi) or in its low level when the former is lower than the latter (AI<VRi) That is, the outputs Si of the lower comparators
10
i
with respect to the analog voltage AI are in its high level while the outputs Si of the higher comparators
10
i
with respect to the same are in its low level.
As soon as the signals S
1
through Sn output from the comparators
10
1
through
10
n
become stable, the controller
2
feeds the clock signal CK
2
to the data latch
3
. In response, the data latch
3
latches the signals S
1
through Sn and then delivers them to the encoder
5
via the error correcting circuit
4
. The encoder
5
transforms the signals CS
1
through CSn output from the error correcting circuit
4
to the binary digital data DO.
As stated above, the conventional parallel comparison type AD converter is capable of converting the analog voltage AI to the digital data DO at the period of the clock signal CK
1
. However, the conventional AD converter leaves the following problems unsolved.
Because the switches
11
and
12
of each comparator
10
i
are implemented by semiconductor switches, they are momentarily rendered conductive with a relatively low resistance at the same time during switching between the ON state and OFF state thereof. As a result, a penetrating current flows between the analog voltage AI and the reference voltage VRi to cause the potential on the node N
1
to vary, lowering the conversion accuracy of the AD converter.
Further, if the difference in level between the analog voltage AI and the reference voltage VRi is small, a sufficient gain is not available with the inverter
14
of each comparator
10
1
. As a result, the output voltage of the inverter
14
becomes the threshold voltage VT to obstruct accurate detection. Moreover, the above penetrating current is apt to continuously flow from the power source potential VDD to the ground potential GND, aggravating power consumption.
Moreover, all the comparators
10
i
operate at the same time without regard to the level of the analog voltage AI. This further aggravates power consumption due to the operation of needless ones of the comparators
10
i
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an AD converter having high conversion accuracy and capable of saving power.
An AD converter of the present invention includes a reference voltage generating circuit for dividing a voltage between a first and a second reference potential to thereby generate a plurality of low reference voltages of a low level, a plurality of high reference voltages of a high level, and a plurality of medium reference voltages of a medium level. A first voltage comparator compares lower one of the medium reference voltages and an analog voltage input to the AD converter and outputs a first control signal if the analog voltage is higher than the lower medium reference voltage. A second voltage comparator compares higher one of the medium reference voltages and the analog voltage and outputs a second control signal if the analog voltage is lower than the higher medium reference voltage. In response to the second control signal, a plurality of third voltage comparators each compare particular one of the low reference voltages and the analog voltage. A plurality of fourth voltage comparators each compare particular one of the medium voltages and the analog voltage. In response t

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