Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2002-11-12
2004-03-16
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000, C341S172000
Reexamination Certificate
active
06707403
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an analog to digital converter (ADC), and in particular, though not limited to a switched capacitor ADC, which comprises a calibration circuit for compensating for coupling capacitor errors in the ADC, and the invention also relates to a method for calibrating the ADC.
BACKGROUND OF THE INVENTION
Switched capacitor ADCs for converting a sampled analog voltage of an input signal to a digital output word are known. Such ADCs comprise a capacitor array, which comprises a plurality of binary weighted capacitors which are selectively chargeable through a switch network under the control of switch bits outputted by a successive approximation register (SAR) in response to the output of a comparator which compares the voltage of the capacitor array with a reference voltage. The switch bits outputted by the SAR progressively switch in and out capacitors of the capacitor array until the voltage on the capacitor array is equal to the reference voltage. The digital word formed by the switch bits outputted by the SAR when the respective voltages on the comparator are equal to each other, within the resolution of the ADC, is determined as being the digital word corresponding to the sampled voltage.
In a single stage binary weighted capacitor array the capacitor corresponding to the least significant bit (LSB) is of unit value, namely, 2
0
unit of capacitance. The capacitor corresponding to the next LSB is of capacitance 2
1
units of capacitance, and so on up to the capacitor corresponding to the most significant bit (MSB), which in an n bit ADC is of 2
n−1
units of capacitance. Typically, each capacitor of the capacitor array is provided by the appropriate number of unit capacitors, each of 2
0
unit capacitance, for example, the capacitor corresponding to the LSB comprises one capacitor of 2
0
unit capacitance, and the capacitor corresponding to the MSB comprises 2
(n−1)
capacitors, each of 2
0
unit capacitance. Accordingly, ADCs with high resolution, for example, resolutions beyond eight bits, require an impracticably large number of unit capacitors. This leads to two problems. Firstly, the total capacitance of the array becomes so large that the voltages of the analog input signal and the reference voltage source are unable to drive the array at a reasonable speed, and secondly, the area of silicon on an integrated circuit (IC) chip required for the capacitors becomes uneconomically large. A reduction in the unit capacitor size, which to some extent would assist in overcoming these problems, in general, leads to the ratio accuracy of the ADC being compromised. To overcome these problems and to facilitate the provision of higher resolution ADCs, series-coupled array ADCs are provided.
In a series-coupled array, the capacitor array is divided into at least two capacitor arrays which are capacitively coupled. One of the capacitor arrays is a most significant array and comprises a capacitor array which represents the MSBs, and the second capacitor array is a least significant array comprising an array of capacitors which represent the LSBs. More than two capacitor arrays may be provided, and each capacitor array is capacitively coupled to the next more significant capacitor array. The value of each coupling capacitor which couples one capacitor array to the next more significant capacitor array depends on the parasitic capacitance in the lesser significant of the two capacitor arrays. Such parasitic capacitance is associated with each portion of the capacitor array, and the ideal value of the coupling capacitor C
c
in a two array ADC is:
C
c
=
C
1
(
C
2
(
2
L
-
1
)
+
C
s2
C
2
2
L
-
C
1
)
where C
1
is the unit capacitance in the most significant capacitor array C
2
is the unit capacitance in the least significant capacitor array C
s2
is the parasitic capacitance associated with the least significant capacitor array and L is the number of capacitors in the least significant capacitor array.
Accordingly, it can be seen from the above equation that the capacitive value of the coupling capacitor for coupling a capacitor array with the next more significant capacitor array is dependent on the parasitic capacitance of the less significant capacitor array. When selecting the capacitance of the coupling capacitor, the capacitance is selected in order to compensate for the parasitic capacitance in the less significant capacitor array of the two capacitor arrays which are coupled by the coupling capacitor. However, due to processing variations in the fabrication of an ADC on silicon in an IC chip, the parasitic capacitance, and indeed the capacitance of the coupling capacitor can vary from chip to chip. Thus, there is a need for a calibration circuit for facilitating adjustment of the effective capacitance of the coupling capacitor between a less significant capacitor array and its next more significant capacitor array, for compensating for silicon and processing variations.
U.S. Pat. No. 5,434,569 of Yung, et al provides such a calibration circuit. Yung discloses a switched capacitor ADC which comprises a two array series-coupled capacitor circuit comprising a most significant capacitor array and a least significant capacitor array. The respective capacitor arrays are capacitively coupled by a coupling capacitor. The calibration circuit comprises an array of binary weighted calibration capacitors which are capacitively coupled to the least significant capacitor array through a small capacitor. A switch network is provided for selectively and alternately switching the calibration capacitors to the most significant capacitor array or to a reference voltage. By switching selected ones of the calibration capacitors to the most significant capacitor array the total capacitance value of the capacitive coupling between the least significant capacitor array and the most significant capacitor array can be increased to a value to compensate for under capacitance of the coupling capacitor, and in turn to compensate for the parasitic capacitance in the least significant capacitor array.
While the provision of the calibration circuit in the ADC of Yung is adequate for compensating for under capacitance of the coupling capacitor, it is unsuitable for correcting for over capacitance of a coupling capacitor.
There is therefore a need for an ADC which comprises a calibration circuit which overcomes the problems of prior art calibration circuits.
The present invention is directed towards providing such an ADC, and the invention is also directed towards providing a method for calibrating an ADC.
SUMMARY OF THE INVENTION
According to the invention there is provided an analog to digital converter (ADC) comprising:
a first capacitor circuit from which a digital output word is derived corresponding to a sampled analog voltage from an input signal, the first capacitor circuit comprising at least two capacitor arrays of progressively increasing significance, each capacitor array being capacitively coupled to the next more significant capacitor array,
a second capacitor circuit,
a comparator having a first input coupled to the most significant capacitor array, and a second input coupled to the second capacitor circuit, and
a first calibration circuit comprising an array of first calibrating capacitors, coupled to one of the capacitor arrays of the first capacitor circuit which is less significant than the most significant capacitor array, the first calibrating capacitors being selectively coupleable to the second input of the comparator for compensating for capacitance errors in the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and the next more significant capacitor array.
In one embodiment of the invention the first calibrating capacitors of the first calibration circuit are selectively coupleable to the first input of the comparator for compensating for capacitance errors in the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and
Analog Devices Inc.
Jean-Pierre Peguy
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