Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-03-13
2003-05-27
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S154000
Reexamination Certificate
active
06570523
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to analog to digital converters, and more particularly to an analog to digital converter that utilizes subranging and interpolation in a pipelined architecture that converts analog samples into corresponding digital values.
DESCRIPTION OF RELATED ART
Analog to digital converters (ADCs) perform a common and basic function that is necessary in many different types of applications. The primary function of an ADC is to convert an analog input signal to a digital value or binary code for use by various circuits and electronic devices. ADCs range in size, complexity, and accuracy or resolution, where each of these factors depend upon the particular needs of the underlying application. An ADC in accordance with the present invention is illustrated for an application that requires a relatively high degree of accuracy and resolution. It is appreciated, however, that although embodiments of the present invention enable such capabilities, the present invention is not limited to any particular types of ADCs or their applications but instead is applicable to any ADC and application regardless of specific requirements.
Embodiments of the present invention may be employed, for example, in a cellular telephone base station in which it is desired to detect and resolve a broad range of signals in a wireless infrastructure. Within a given cell of a cellular infrastructure, different cell phones operate at different power levels and frequencies. The ADC employed at the front end of the base station must be able to digitize the entire bandwidth of operation to service all cellular phones within its cell. The cell phones are mobile and at variable distances from the base station. The base station must be able to resolve the “near-far” issue and detect all signals within the cell regardless of distances and power levels, and must be able to distinguish between strong and relatively weak signals.
It is desired that an ADC employed in a cellular base station application digitize an input analog signal with a very high degree of accuracy. The ADC should exhibit a high degree of linearity, have a relatively high resolution with a high signal to noise ratio (SNR). In the cellular base station application, for example, it is desired that the ADC have a resolution of 14 bits with a spurious free dynamic range (SFDR) of 105 dBc and with an SNR of greater than 75 dB and operate at a Nyquist rate of approximately 80 MHz to accurately represent an input signal with a bandwidth of 40 MHz. Such 14-bit resolution is analogous to being able to distinguish the approximate thickness of a human hair on an 8 foot wall. The requisite SFDR enables determination of whether the variation of the thickness of the hairs laid over the entire 8 foot wall is no more than 10% of the nominal thickness (assuming the wall is perfectly flat).
ADCs are commonly integrated into a monolithic unit on one substrate of an integrated circuit (IC) or chip. Silicon, however, only allows up to about 10 bits of matching and is insufficient alone to achieve higher resolution. Correction and calibration techniques are known to improve the resolution, such as laser trimming or fuse blowing. Such post-processing techniques, however, must be performed on a part-by-part basis thereby unduly complicating and increasing cost of the manufacturing process. Also, such post-processing techniques operate under fixed conditions and do not correct for inaccuracies or changes due to temperature, aging and/or operating conditions. Integrated calibration techniques are also known and usually operate to measure error at the backend and apply a correction factor. Such calibration techniques are limited by quantization and are usually limited correction to one-half bit of resolution of the converter itself. Also, the calibration techniques are incorporated in silicon and thus subject to the same limitations of the target circuitry.
Many ADC techniques and architectures are known. Some of the early ones were used in the low resolution converters. Flash conversion is a classical technique where the input signal is compared to a reference voltage and the result is decoded into a digital word. The flash needs 2
N
comparators where N is the number of bits of resolution. As a result, the number of comparators and the power consumption exponentially increase with higher resolution. Although some improvements have been made, practical solutions are limited to about 8 bits of resolution to achieve optimum performance.
Pipeline converters behave similarly to flash converters except that there is a finite latency between the analog sample and the digital representation of the sample, which is dependent on the number of stages in the pipeline. The matching of the elements in the converter is limited to approximately 10 bits, beyond which some calibration of the components is required in any architecture. When the resolution is increased, the input stages have to be more accurate in resolving the input signal, which results in slower conversion speeds because of the settling time of the amplifier. Time interleaving of multiple pipeline converters has been demonstrated. This technique is limited by the accuracy of the sampling interval relative to the other stages, the relative gain and offset match, and the timing jitter of the sampling clocks
Successive approximation converters also allow higher resolutions but tend to be slower since they usually require N cycles to produce the answer. Sigma delta techniques allow much higher resolutions (10 to 24 bits), but are relatively slow since the requisite level resolution is achieved by oversampling the input signal and noise shaping. Folding is another high speed technique in which the signal is “folded” by using several folding amplifiers to replicate the input signal and by detecting zero crossings of the folding amplifiers to produce the digital output. Again, for higher resolution, the folding technique requires many folding amplifiers resulting in relatively high power consumption. Furthermore, the folding amplifiers must be faster by a factor that is equivalent to the folding ratio used in the converter. Higher resolution folding also requires calibration. Although interpolation, when used with folding, reduces the number of folding amplifiers, the resulting dynamic range of the converter is also limited.
SUMMARY OF THE INVENTION
An analog to digital converter (ADC) in accordance with embodiments of the present invention performs subranging and interpolation to convert an input analog signal into a stream of output digital values with a predetermined resolution. It is appreciated that an ADC according to at least one embodiment of the present invention may be implemented using a pipelined architecture with multiple sequential stages to resolve the digital value. The ADC may include, for example, a sampler that regularly samples an input analog signal and that provides a stream of sample signals to a first stage. The ADC further includes at least one secondary stage, where each secondary stage is coupled in sequential order after the first stage. The ADC also includes an error corrector or combiner that combines the digital results of the stages and generates a corresponding stream of digital values.
The first stage flash converts the stream of sample signals into corresponding primary multiple bit values and subranges a reference ladder for each primary multiple bit value into corresponding sets of reference signals. Each secondary stage is coupled in sequential order after the first stage. Each secondary stage amplifies each set of residual signals from a prior stage, interpolates each set of amplified residual signals using a resistive ladder, flash converts each set of amplified residual signals into corresponding secondary multiple bit values, and chooses the correct subrange of residual signals for each corresponding secondary multiple bit value. The final stage amplifies each set of residual signals from a prior stage and flash converts each set of amplified residua
Allen Brian L.
Bacrania Kantilal
Chen Hsin-Shu
Hakkarainen J. Mikko
Sanchez Mario
Intersil America's Inc.
Stanford Gary R.
Wamsley Patrick
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