Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1998-12-15
2001-03-06
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S120000
Reexamination Certificate
active
06198423
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic systems, and more particularly, to an improved analog-to-digital converter system having enhanced digital self-calibration capabilities.
BACKGROUND OF THE INVENTION
Analog-to-digital converter systems can be used to convert continuously varying signals such as analog representations of sound into digital codes for storage and for processing in the digital domain. One popular architecture for analog-to-digital converter systems is an algorithmic analog-to-digital converter. Algorithmic analog-to-digital converters can be implemented using modern CMOS technology using switched capacitor techniques. In these architectures, accurate conversion of an analog signal to a digital representation relies on the assumption that the capacitors in the switched capacitor array all have the same capacitive value. No matter how good the processes used to create the capacitors, this is not an entirely valid assumption. The mismatch in the capacitors effects the resolution of the algorithmic analog-to-digital converter. This capacitor mismatch is typically expressed as a number of bits and with modern CMOS technology the capacitor matching is typically 8-10 bits.
One technique to improve the resolution of an analog-to-digital converter is through the use of digital calibration. In this approach, a calibration cycle is performed to measure an error due to the mismatch of the capacitors in the system. The digitized error quantity is stored in a memory system. Calibration logic can then take the stored error quantity and compute a necessary correction to the output of the analog-to-digital converter.
Although certainly more effective than non-calibrated systems, systems that use this calibration technique have a limited tolerance to capacitor mismatch due to the fact that they use a non-calibrated system to estimate the error voltage. In addition, these systems have typically only been applied to single stage or 1.5 bits per stage converter architectures.
Algorithmic analog-to-digital converter systems that resolve more than a single bit per stage are much more efficient for certain applications and, as such, the inability to use the calibration techniques on these multi-bit architectures is an important weakness in prior systems.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an analog-to-digital converter architecture that allows for digital self-calibration but reduces first order error in the calibration and allows for calibration in multibit converter architectures that resolve multiple bits per stage.
In accordance with the teachings of the present invention an analog-to-digital converter architecture is provided that substantially reduces or eliminates disadvantages associated with prior systems and techniques. According to one embodiment of the present invention, a method of operating an analog-to-digital converter is provided that comprises the step of sampling a reference signal having a known voltage. The method then digitizes the sampled voltage using a multi-stage, analog-to-digital converter to yield a first order digitized error value that is a function of the mismatch between the capacitive values of capacitors within the analog-to-digital converter. The method then proceeds to calculate a second order digital error value by using the first order digital error value to correct partially the value of the digitized input voltage in the equation for the digital error value. The second order digital error value can then be used to correct the digitized output values of analog input signals having unknown voltage levels during the later operation of the analog-to-digital converter.
According to an alternate embodiment of the present invention, the multi-order calculation of a digital error value can be used in an analog-to-digital converter having the ability to resolve multiple bits of a digitized value in a single stage of the analog-to-digital converter.
According to an alternate embodiment of the present invention, the digital error value can be calculated in an iterative fashion. For example, the second order digital error value can be used to calculate in an identical manner a third order digital error value. This process can continue to an arbitrary order to iteratively increase the accuracy of the digital error value.
REFERENCES:
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patent: 5416485 (1995-05-01), Lee
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Brady III Wade James
Nguyen John
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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