Analog-to-digital converter having positively biased...

Details Analog-to-digital converter having positively biased... Analog-to-digital converter having positively biased...

2000-11-01

2003-01-07

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S154000, C341S156000, C341S118000, C327S052000, C327S063000, C327S081000, C327S085000

Reexamination Certificate

active

06504499

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to analog-to-digital conversion and, in particular, to an analog-to-digital converter having positively biased differential reference voltage inputs.
2. Description of the Related Art
With reference to
FIG. 1
, there is depicted a circuit diagram of a prior art analog-to-digital converter (ADC) that is disclosed in U.S. Pat. No. 5,731,776 to Kumamoto et al. As shown, ADC
102
includes a resistor ladder
1
, eight differential comparators C
1
-C
8
, an encoder
10
, and a control unit
15
. Resistor ladder
1
has a lower voltage reference terminal
2
having reference voltage VRB, an upper voltage reference terminal
3
having reference voltage VRT, and identical resistors r
1
-r
9
connected in series there between. At the junctions of resistors r
1
-r
9
, intermediate taps T
1
-T
8
provide a number of intermediate reference voltages.
Differential comparators C
1
-C
8
each have an output connected to encoder
10
and four input terminals, two inverting reference input terminals connected to taps in resistor ladder
1
and two analog voltage input terminals. In general, for the differential comparator C(i)(i=1 . . . 8), the positive reference input terminal is connected to the intermediate tap T(i) provided at the junction between the resistors r(i) and r(i+1), and the negative reference input terminal is connected to the intermediate tap T(
9
−i) provided at the junction between the resistors r(
10
−i) and r(
9
−i). In other words, the positive reference input terminal of the differential comparator C(i) and the negative reference input terminal of the differential comparator C(
9
−i) are connected in common to the intermediate tap T(i). It is important to note that this arrangement results in an inversion of the reference voltage input terminals, with the positive reference voltage terminal of half of the comparators tied to a lower reference voltage than the negative reference voltage terminal. For each of differential comparators C
1
-C
8
, the positive analog voltage input terminal is connected to a differential input signal line
6
having analog voltage Vi, and the negative analog voltage input terminal is connected to a differential input signal line
5
having the complementary analog voltage Vi*.
In operation, each of differential comparators C
1
-C
8
compares the difference between analog input voltages Vi and Vi* with the difference between the reference voltages applied to its inverting reference voltage inputs and outputs a digital signal indicative of the comparison result. In other words, each of differential comparators C
1
-C
8
amplifies the difference between (V
in+
−V
in−
) and (−V
ref+
(−V
ref−
) ) and outputs the amplified difference. Thus, an output voltage signal V
out
generated by each of differential comparators C
1
-C
8
is expressed as V
out
=G×((V
in+
−V
in−
)−(−V
ref+
−(−V
ref−
))), where G is the gain of the comparator.
Because the resistances of resistors r
1
-r
9
are equal, the value of divided reference voltage (−V
ref+
−(−V
ref−
)) increases in equal intervals in the order of differential comparators C
1
-C
8
. Thus, if the difference between the input voltage signals Vi and Vi* is higher than the divided reference voltage between intermediate taps T
2
and T
7
and lower than the divided reference voltage between intermediate taps T
3
and T
6
, the difference between the input voltage signals Vi and Vi* is higher than the divided reference voltages applied to differential comparators C
1
-C
2
and lower than the divided reference voltages applied to differential comparators C
3
-C
8
. Consequently, differential comparators C
1
-C
2
output logic high signals and differential comparators C
3
-C
8
output logic low signals. Encoder
10
encodes the signals output by differential comparators C
1
-C
8
into a three-bit digital signal and a one-bit overflow indication. In this manner, ADC
102
converts the analog differential input voltage signals Vi and Vi* into a digital signal.
Although the design of ADC
102
is advantageous in terms of semiconductor chip floor planning in that the wiring length between taps T
1
-T
8
and the associated differential comparators C
1
-C
8
is minimized, ADC
102
is subject to a number of drawbacks appreciated by the present invention. In particular, the inversion of reference voltage inputs to differential comparators C
1
-C
4
negatively biases the comparator circuitry and can create asymmetry in the voltage differences generated by comparator pairs C
1
and C
8
, C
2
and C
7
, C
3
and C
6
and C
4
and C
5
for certain comparator designs. Such voltage asymmetry can yield asymmetrical conversion results for analog voltages of equivalent magnitude and opposite sign. In addition, for at least some comparator designs, the inversion of the reference voltage inputs can disadvantageously reduce both the dynamic voltage range of the transistors comprising the comparator and the differential gain. As will be appreciated, as lower power integrated circuits having lower reference voltages are designed, the differential gain provided by the differential comparators becomes increasing important in order to correctly quantize analog signals with high precision.
SUMMARY OF THE INVENTION
The present invention addresses and overcomes the foregoing and other shortcomings of the prior art by providing an improved analog-to-digital converter (ADC) having positively biased reference voltage inputs.
An analog-to-digital converter in accordance with the present invention includes a plurality of comparators that each have an output, two analog data inputs coupled to a differential analog data input, and two reference voltage inputs. The two reference voltage inputs are each coupled to a resistor ladder that contains a plurality of resistors coupled in series. Importantly, the two reference voltage inputs of each comparator are positively biased, meaning that the positive reference voltage input is coupled to a point on the resistor ladder at a relatively higher potential than the negative reference voltage input. The outputs of the comparators are coupled to an encoder that encodes signals at the outputs into a digital signal. By positively biasing the differential reference voltage inputs of the comparators in this manner, the differential gain, dynamic voltage range, and voltage symmetry of the comparators are advantageously improved.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


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patent: 5734342 (1998-03-01), Mes
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patent: WO92/08287 (1992-05-01), None
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