Analog-to-digital converter having output data with reduced...

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C341S118000, C341S120000, C341S131000, C341S143000, C341S144000

Reexamination Certificate

active

07978113

ABSTRACT:
A circuit includes an analog-to-digital converter configured to receive an analog input signal and generate first digital values at a first sampling rate. The first digital values have a first bit-width. The circuit also includes an interpolator configured to receive the first digital values and generate second digital values at a second sampling rate higher than the first sampling rate. The second digital values have a second bit-width equal to or greater than the first bit-width. The circuit further includes a digital filter configured to receive the second digital values and perform bit-width reduction in a recoverable manner to generate third digital values. The third digital values have a third bit-width less than the first and second bit-widths. The circuit could optionally include a recovery circuit configured to process the third digital values to generate recovered digital values at the first sampling rate. The recovered digital values have the first bit-width.

REFERENCES:
patent: 5561425 (1996-10-01), Therssen
patent: 5748126 (1998-05-01), Ma et al.
patent: 6005506 (1999-12-01), Bazarjani et al.
patent: 6215423 (2001-04-01), May et al.
patent: 6326912 (2001-12-01), Fujimori
patent: 6501406 (2002-12-01), Mecchia et al.
patent: 6587011 (2003-07-01), Mellot
patent: 6987953 (2006-01-01), Morris et al.
patent: 7109906 (2006-09-01), Zoso et al.
patent: 7194036 (2007-03-01), Melanson
patent: 7619551 (2009-11-01), Wu
patent: 7809047 (2010-10-01), Kummetz
patent: 2002/0018012 (2002-02-01), Nakao et al.
patent: 2002/0042256 (2002-04-01), Baldwin et al.
patent: 2006/0087466 (2006-04-01), Domingo
patent: 2007/0252737 (2007-11-01), Eikenbroek
patent: 2008/0205557 (2008-08-01), He
“Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost”, Texas Instruments, Apr. 2009, 68 pages.
“Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs”, Texas Instruments, Jan. 2008, 64 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Analog-to-digital converter having output data with reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Analog-to-digital converter having output data with reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Analog-to-digital converter having output data with reduced... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2639360

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.