Analog-to-digital converter having multi-bit cascaded sigma-delt

Details Analog-to-digital converter having multi-bit cascaded sigma-delt Analog-to-digital converter having multi-bit cascaded sigma-delt

1992-03-20

1993-12-28

Pellinen, A. D.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

375 26, H03M 304

Patent

active

052743748

ABSTRACT:
A multi-bit cascaded sigma-delta A/D converter (40) has a higher resolution, higher sample rate, and lower harmonic distortion than previous multi-bit cascaded sigma-delta approaches. The A/D converter employs delaying switched capacitor integrators to relax settling time requirements and to thereby ease op amp design for multi-bit cascaded sigma-delta A/D converters. The converter has a true sample and hold input; the op amp amplifies a fixed amount of charge; and nodes are settled with the dc gain of the op amp, permitting greater settling accuracy.

REFERENCES:
patent: 5148166 (1992-09-01), Ribner
patent: 5159341 (1992-10-01), McCartney et al.
"Architectures for High-Order Multibit Modulators" R. Walden et al. 1990 IEEE International Symposium of Circuits and Systems, May 1-3, 1990.

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