Analog-to-digital converter having high AC line noise rejection

Details Analog-to-digital converter having high AC line noise rejection Analog-to-digital converter having high AC line noise rejection

1992-12-21

1994-09-20

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

341166, H03M 302

Patent

active

053493524

ABSTRACT:
Analog-to-digital (AID) converters with power line frequency noise rejection by synchronization of the converter clock with the power line frequency through a phase locked loop. Both sigma delta and integrating A/D converters may use the synchronized clock to precisely reject power line frequency noise.

REFERENCES:
patent: 4195235 (1980-03-01), Schoeff
patent: 4595906 (1986-06-01), Bingham
patent: 4833474 (1989-05-01), Nagai et al.
patent: 4972436 (1990-11-01), Halim et al.
patent: 5157395 (1992-10-01), Del Signore et al.
patent: 5179380 (1993-01-01), White
patent: 5198817 (1993-03-01), Walden et al.

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