Coded data generation or conversion – Converter compensation
Reexamination Certificate
1999-12-09
2002-03-19
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S120000
Reexamination Certificate
active
06359575
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the art of analog-to-digital (A/D) converters and digital-to-analog (D/A) converters.
DESCRIPTION OF THE RELATED ART
Analog-to-digital converters (ADCs) are circuits used to convert signals from the analog domain, where the signals are represented by continuous quantities such as voltage and current, to the digital domain, where the signals are represented by numbers. These circuits can be implemented in a large number of ways. Established A/D conversion techniques include flash, delta-sigma (or sigma-delta), sub-ranging, successive approximation, and integrating.
ADC's typically include an internal digital to analog (D/A) converter. The D/A converter may be comprised in a feedback loop in the ADC. One example of an A/D converter is an over-sampled A/D converter. Oversampled A/D converters, often denoted as “delta-sigma converters” or “sigma-delta converters” are well known in the art. A delta sigma (D/S) converter essentially digitizes an analog signal at a very high sampling rate (oversampling) in order to perform a noise shaping function. The digitized signal is provided to an internal D/A converter to produce an analog signal, which is then supplied through a feedback loop to be combined with the analog input signal.
FIG. 1
shows, in block diagram form, a D/S converter
10
commonly known in the art. The D/S converter
10
may be a single bit or multi-bit delta sigma converter. The D/S converter
10
includes a D/S modulator
12
connected to a digital filter and decimation circuit
14
. The D/S modulator
12
includes a summing node
16
, a filter
18
, an A/D converter
20
, and a D/A converter
22
. The D/A converter
22
is connected to the output of the A/D converter
20
and operates to provide feedback to the summing node
16
. The summing node
16
includes a pair of inputs, one being connected to the analog input signal V
in
and the other being connected to the output of the D/A converter
22
.
In operation, the output of summing node
16
is low-pass filtered by filter
18
and subsequently converted into a digital signal by A/D converter
20
. The digital signal in turn is converted back into an analog signal by D/A converter
22
and subtracted from analog input signal V
in
at summing node
16
.
The D/S modulator
12
converts the input signal V
in
into a continuous serial bit stream at a rate determined by sampling clock frequency, kf
s
. Due to the feedback provided by the D/A converter
22
the average value output by the D/A converter
22
approaches that of the input signal V
in
if the loop has enough gain.
A multi-bit D/S converter provides benefits over a single bit D/S converter implementation. Namely, a multi-bit D/S converter provides more resolution and less quantization noise. Additionally, a multi-bit D/S converter is more stable than single bit D/S converter. However, the multi-bit D/S converter suffers from linearity errors introduced by the internal multi-bit D/A converter.
Linearity error is the inability of the multi-bit D/A converter to accurately translate a digital input value into an analog current or voltage. In other words, given a particular digital input, the resulting analog output of the multi-bit internal D/A converter
62
approximates the digital value but is not exactly equal to the digital value. In reality, the actual analog output differs from the digital input value by an amount equal to the linearity error.
FIG. 2
shows a graphical comparison of an ideal linear vs. non-ideal, non-linear multi-bit D/A converter. The horizontal axis represents the codes or multi-bit digital signals applied to the inputs of both types of multi-bit D/A converters, ideal and non-ideal. The vertical axis represents the analog signal output therefrom. Line L represents the transfer function of the ideal or linear D/A converter. Line NL represents the transfer function of the non-ideal or non-linear D/A converter. Variations between the two lines represent the linearity errors. The distance between points on a vertical line through both line L and the line NL represent the linearity error produced by the non-ideal D/A converter for a particular input code. For example, if digital code x is input to both the ideal D/A converter and the non-ideal D/A converter, the respective outputs would be Y
L
and Y
NL
. The difference in voltage &Dgr;Y represents the linearity error corresponding to digital code x. This linearity error is viewed as noise and degrades the ultimate signal to noise ratio of the D/S converter which contains the non-linear D/A converter. This linearity error is static in nature and independent of frequency and voltage.
The source of linearity errors can be traced to the internal current generators of the multi-bit D/A converter.
FIG. 3
shows, in schematic form, a simplified D/A converter
70
employing a number of internal current generators
72
. Each of the internal current generators
72
is selectively connected to an output node
74
via switches
76
. Each switch
76
contains an input configured to receive one bit of the digital code inputted to the D/A converter
70
. For example, switch S
N-1
is controlled by the most significant bit of the input digital code. When the most significant bit is
1
, the associated current generator is connected to summing node
74
. Thus, given a particular digital input code, the output of one or more of the current generators
72
is connected to the summing node
74
.
If the D/A converter
70
was ideal and contained ideal current generators, current would be generated therefrom in integer units. For example, if the D/A converter
70
of
FIG. 3
was an ideal 3 bit D/A converter, and a digital code inputted thereto equaled
111
, the three ideal internal current generators
72
would generate 4, 2, and 1 units of current, respectively. However, internal current generators are rarely ideal. Given an input code
111
, the non-ideal set of current generators, for example, might generate 4.05, 1.98, and 1.01 units of current, respectively.
The linearity error produced by the internal current generators can be further traced to a variety of causes, chief of which is the inability of integrated circuit manufacturers to form, in silicon, current generators having identical geometries. Several other causes can be related to the linearity error. Over time and use, the internal current generators may wear differently. Moreover, temperature variations may occur between the internal current generators. In any event, the physical differences between internal current generators in a D/A converter, even though slight, can produce significant errors in the translation of a digital input code into an analog equivalent.
U.S. Pat. Nos. 5,781,137 and 5,781,138 describe a system and method which operate to calibrate the internal D/A converter of a multi-bit A/D converter to eliminate or otherwise reduce linearity errors in the multi-bit A/D converter. The technique disclosed in these patents includes applying a known analog waveform, such as a pure sine wave, to an input of the A/D converter, or to a portion of the A/D converter, and generating digital signals representative of the pure sine wave. A number of the digital signals output from the converter are recorded. These recorded digital signals contain hidden information regarding the linearity errors associated with the internal D/A converter of the A/D converter. The linearity error information can be extracted and used in deriving correction coefficients and constructing a linearity error correction circuit. The linearity error correction circuit then can be used to correct for linearity errors in the A/D converter.
The system and method described in the above patents operate to calibrate the internal D/A converter and remove linearity errors from the internal D/A converter. Once the internal D/A converter has been calibrated, it would be more desirable to more fully take advantage of the internal D/A converter for other purposes.
SUMMARY OF THE INVENTION
The present invention comprises an an
Conley Rose & Tayon PC
Hood Jeffrey C.
National Instruments Corporation
Wamsley Patrick
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