Analog to digital converter, encoder, and recorded data...

Details Analog to digital converter, encoder, and recorded data... Analog to digital converter, encoder, and recorded data...

2000-05-09

2001-09-11

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S172000, C341S159000

Reexamination Certificate

active

06288665

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to Analog to Digital (A/D) converters for converting analog signals to a digital signals, and to a recorded data reproducing apparatus for reading out write data from a recording medium.
2. Description of the Related Art
Recently, A/D converters have been used in various electronic devices which have a growing demand for faster A/D conversion. A typical A/D converter comprises a plurality of comparator sections for comparing analog input signals with analog reference voltages and an encoder section for converting the output signals of the comparator sections to digital signals consisting of a plurality of bits. To increase A/D conversion speed, it is necessary to improve the operation speeds of both the comparator sections and the encoder sections.
One type of A/D converter is a parallel type A/D converter, which is superior to other types of A/D converters in terms of A/D conversion speed.
FIG. 1
shows a conventional parallel type A/D converter, which outputs a 5-bit digital output signal. Thirty-two resistors R are connected in series between a high-potential reference voltage supply VRH and a low-potential reference voltage supply V
RL
. Each of the two resistors R respectively located at the top and bottom ends of the resistor series circuit has half the resistance of each of the other thirty resistors R.
The A/D converter includes thirty-one comparators CM
1
to CM
31
each having first and second input terminals. Thirty-one nodes between the thirty-two resistors R are connected to the first input terminals of the comparators CM
1
-CM
31
, respectively. Therefore, the individual comparators CM
1
-CM
31
are respectively supplied with reference voltages V
R1
to V
R31
, which are determined by dividing the potential difference between high and low reference voltages V
RH
and V
RL
by the resistors. An analog input signal A
in
is supplied to the second input terminals of the comparators CM
1
-CM
31
. The comparators CM
1
-CM
31
operate based on a control signal output from a control circuit (not shown) and compare the analog input signal A
in
with the respective received reference voltage signal V
R1
-V
R31
.
The comparators CM
1
-CM
31
have an identical structure and the internal circuit of each comparator is illustrated in FIG.
2
. The first and second input terminals receive a reference voltage V
R
and an analog input signal A
in
, respectively, and are connected to a node N
13
which is the first terminal of a capacitor C
3
via switch circuits SW
11
and SW
10
, respectively. The switch circuits SW
10
and SW
11
are controlled by a pair of associated control signals CS
4
and CS
5
provided by the aforementioned control circuit, and are switched on when the associated control signals CS
4
and CS
5
are high.
A node N
14
represents a second terminal of capacitor C
3
which is connected to the input terminal of an inverter circuit
4
h
whose output terminal is connected to its input terminal via a switch circuit SW
12
. The switch circuit SW
12
is controlled based on the control signal CS
4
, and is switched on when the control signal CS
4
goes high. The output signal of the inverter circuit
4
h
is supplied via a capacitor C
4
to an inverter circuit
4
i whose input and output terminals are connected together via a switch circuit SW
13
. The switch circuit SW
13
is controlled by the control signal CS
5
, and is switched on when the control signal CS
5
goes high. An output signal S is output by the output terminal of the inverter circuit
4
i
and is also inverted by an inverter circuit
4
j
, yielding an output signal /S.
The operation of the comparator CM shown in
FIG. 2
will be now described with reference to FIG.
3
. When control signal CS
5
is at a L (Low) level and control signal CS
4
is at a H (High) level, the switch circuit SW
11
is switched off and the switch circuits SW
10
, SW
12
and SW
13
are switched on. As a result, the potentials at node N
14
and the output terminal of the inverter circuit
4
h
are reset to a threshold voltage of the inverter circuit
4
h
. This causes the charge current to flow into the capacitor C
3
and causes the potential at node N
13
to become the potential level of the analog input signal A
in
. The potentials at the input and output terminals of the inverter circuit
4
i
are reset to a threshold voltage of the inverter circuit
4
i.
When the control signal CS
4
goes low and the control signal CS
5
goes high, the switch circuits SW
10
, SW
12
and SW
13
are switched off and the switch circuit SW
11
is switched on. Consequently, the reference voltage V
R
is compared with the potential level of the analog input signal A
in
. When the reference voltage V
R
is higher than the potential level of the analog input signal A
in
, the potential at node N
14
becomes higher than the threshold voltage of the inverter circuit
4
h
due to capacitive coupling by the capacitor C
3
, and the output signal of the inverter circuit
4
h
becomes low. As a result, the potential level on the input side of the inverter circuit
4
i
becomes lower than the threshold voltage of this inverter circuit
4
i
due to capacitive coupling by the capacitor C
4
. Consequently, the output signal S goes high and the output signal /S goes low.
When the reference voltage V
R
is lower than the potential level of the analog input signal A
in
, the potential at node N
14
becomes lower than the threshold voltage of the inverter circuit
4
h
due to capacitive coupling by the capacitor C
3
, and the output signal of the inverter circuit
4
h
goes high. As a result, the potential level on the input side of the inverter circuit
4
i
becomes higher than the threshold voltage of this inverter circuit
4
i
due to capacitive coupling by the capacitor C
4
. Consequently, the output signal S goes low and the output signal /S goes high.
When the control signal CS
4
goes high and the control signal CS
5
goes low, the potential at node N
13
is reset to the potential level of the analog input signal A
in
and the potentials at the input and output terminals of the inverter circuits
4
h
and
4
i
are reset to the threshold voltages of the associated inverter circuits
4
h
and
4
i
. When the levels of the control signals CS
4
and CS
5
are changed, the reference voltage V
R
is (once again) compared with the potential level of the analog input signal A
in
and the above-described operation will be repeated.
When the potential level of the analog input signal A
in
is lower than the received reference voltage (one of V
R1
to V
R31
), each of the comparators CM
1
to CM
31
(each having the internal structure shown in
FIG. 2
) outputs an H (High)-level output signal (one of output signals S
1
to S
31
) and an L (Low)-level output signal (one of signals /S
1
to /S
31
). On the other hand, when the potential level of the analog input signal A
in
is higher than the received reference voltage (voltages V
R1
to V
R31
), each comparator outputs an L-level output signal (one of the signals S
1
to S
31
) and an H-level output signal (one of the signals /S
1
to /S
31
).
For example, when the potential level of analog input signal A
in
is higher than a reference voltage V
R4
but lower than the reference voltage V
R1
, output signals S
1
to S
4
corresponding to comparators CM
1
to CM
4
will go high, while output signals /S
1
to /S
4
will go low. Output signals S
5
to S
31
representing the upper twenty-seven comparators CM
5
to CM
31
will go low while output signals /S
5
to /S
31
go high.
The output signals S
1
-S
31
and /S
1
-/S
31
of the comparators CM
1
-CM
31
are coupled to thirty-two 2-input NOR gates DE
0
to DE
31
, which function as an address decoder. More specifically, the output signals S
1
-S
31
of the comparators CM
1
-CM
31
are supplied to the first input terminals of the NOR gates DE
1
to DE
31
, while the output signals /S
1
-/S
31
of the comparators CM
1
-CM
31
are supplied to the second input terminals of the NOR gates

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