Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2007-12-25
2007-12-25
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S154000, C341S155000
Reexamination Certificate
active
11403845
ABSTRACT:
Disclosed is an analog-to-digital converter circuit that includes a reference circuit for applying reference voltages to comparators that compare the reference voltages with the output of the buffer circuit. The reference circuit includes a first voltage-dividing resistor circuit, which is connected between first and second voltage supply terminals, for supplying the reference voltages to the comparators; a second voltage-dividing resistor circuit connected between the first and second voltage supply terminals in parallel with the first voltage-dividing resistor circuit; first and second buffers having their input ends connected to respective ones of first and second taps of the second voltage-dividing resistor circuit; a first amplifier for receiving and differentially amplifying the output at a first end of the first voltage-dividing resistor circuit and the output of the first buffer; a second amplifier for receiving and differentially amplifying the output at a second end of the first voltage-dividing resistor circuit and the output of the second buffer; a transistor, which is connected between the first voltage supply terminal and the first end of the first voltage-dividing resistor circuit and which has its gate connected to the output of the first amplifier; and a transistor, which is connected between the second voltage supply terminal and the second end of the first voltage-dividing resistor circuit and which has its gate connected to the output of the second amplifier. Reference voltages are supplied to corresponding comparators from the first and second ends of the first voltage-dividing resistor circuit and from taps of resistors connected between said first and second ends.
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“A Duel-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a Converter in a 0.25-um Digital CMOS Process”, IEEE Journal of Solid State Circuits, vol. 35, No. 12, Dec. 2000, pp. 1760-1768.
Jeanglaude Jean Bruner
McGinn IP Law Group PLLC
NEC Electronics Corporation
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