Analog to digital converter built in self test

Coded data generation or conversion – Converter calibration or testing

Reexamination Certificate

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C341S144000, C341S155000

Reexamination Certificate

active

07081841

ABSTRACT:
A built in self test circuit for testing an analog to digital converter. An up counter receives a test input and a first clock signal and provides and upper limit. A down counter receives the test input and the first clock signal, and provides a lower limit. A digital to analog converter receives the test input and a second clock signal, and provides an analog output. Circuitry provides the analog output and a third clock signal to the analog to digital converter, and the analog to digital converter thereby produces a digital signal. An upper limit comparator receives the upper limit and the digital signal, and provides an upper limit status signal indicating whether the digital signal violates the upper limit. A lower limit comparator receives the lower limit and the digital signal, and provides a lower limit status signal indicating whether the digital signal violates the lower limit.

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Arabi et al., “A New Built-in Self-Test Approach for DAC and ADCs”, IEEE/ACM Int'l Conf. on CAD-94, Digest of Technical Papers, IEEE Conputer Society Press, 1994 (no month) pp. 491-494.

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