Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2006-07-25
2006-07-25
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S144000, C341S155000
Reexamination Certificate
active
07081841
ABSTRACT:
A built in self test circuit for testing an analog to digital converter. An up counter receives a test input and a first clock signal and provides and upper limit. A down counter receives the test input and the first clock signal, and provides a lower limit. A digital to analog converter receives the test input and a second clock signal, and provides an analog output. Circuitry provides the analog output and a third clock signal to the analog to digital converter, and the analog to digital converter thereby produces a digital signal. An upper limit comparator receives the upper limit and the digital signal, and provides an upper limit status signal indicating whether the digital signal violates the upper limit. A lower limit comparator receives the lower limit and the digital signal, and provides a lower limit status signal indicating whether the digital signal violates the lower limit.
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Feist Douglas J.
Gearhardt Kevin J.
Savage Scott C.
Jeanglaude Jean Bruner
LSI Logic Corporation
Luedeka Neely & Graham PC
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