Analog-to-digital converter architecture using a capacitor...

Details Analog-to-digital converter architecture using a capacitor... Analog-to-digital converter architecture using a capacitor...

2008-07-22

2008-07-22

Nguyen, Khai M (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S158000, C341S172000

Reexamination Certificate

active

07403150

ABSTRACT:
An analog-to-digital converter architecture is described. An analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure. The comparator device array further includes multiple comparator devices coupled in parallel, each comparator device having a pair of inputs coupled to the switched capacitor circuit structure to receive a voltage output signal from the switched capacitor circuit, a voltage value of the voltage output signal being calculated as a difference between an input voltage value of the input voltage signal and a predetermined value of the reference voltage signal, which is dependent on the position of the respective comparator device within the comparator device array, each comparator device experiencing an identical common mode voltage input within the analog-to-digital converter circuit.

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patent: 5470121 (1995-11-01), Ito
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patent: 2007/0040723 (2007-02-01), Snoeijs
Koen Uyttenhove and Michiel Steyaert—A 1.8-V, 6-bit, 1.3GHz CMOS Flash ADC in 0.25 μm CMOS.ESAT—MICAS K.U. Leuven, Kasteelpark Arenberg 10, 3001 Heverlee, Belgium Tel.: +32 16 32 1070koen.uttenhove@esat.kuleuven.ac.be ESSCIRC 2002, no month.

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