Analog-to-digital converter and method with switched...

Details Analog-to-digital converter and method with switched... Analog-to-digital converter and method with switched...

2006-04-11

2006-04-11

Nguyen, Linh V. (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S172000

Reexamination Certificate

active

07026968

ABSTRACT:
Methods and structures are provided that reduce conversion errors in pipelined analog-to-digital converters which are induced in one converter cycle by component memory of signals in one or more preceding converter cycles. The methods and structures include the use of digital filters that provide a digital representation of the residue of a preceding converter cycle, multiply this representation by an appropriate memory parameter, and sum the product with the digital representation of the residue of a current converter cycle to thereby reduce the memory effect. The methods and structures also form capacitors of switched-capacitor converter structures with sub-capacitors that are reconfigured (e.g., reversed or alternated between differential sides of differential amplifiers) in different converter cycles.

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Zanachi, Alfio, et al., “Impact of Dielectic Relaxation on a 14b Pipeline ADC in 3V SiGe BiCMOS”, Feb. 12, 2003 IEEE International Solid-State Circuits Conference, Session 18—Nyquist A/D Converters.

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