Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2003-09-29
2004-11-02
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000, C341S159000
Reexamination Certificate
active
06812880
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an analog/digital converter and to a method for converting an analog signal into a digital signal.
Analog/digital converters (ADCs) are produced on the basis of the prior art as an integrated circuit utilizing metal oxide semiconductor structures and/or bipolar semiconductor structures on semiconductor substrates as standard. With high demands on the signal processing speed, so called “flash ADCs” are frequently reverted to.
2. Description of the Related Prior Art
As
FIG. 1
shows, a flash ADC based on the prior art is an analog/digital converter
101
which has, by way of example, a resistor cascade containing a plurality of series-connected resistors
102
and a plurality of comparators
103
, with a first input
104
on the comparators
103
being connected between two respective adjacent resistors
102
, as a reference network. A reference voltage U
ref
is applied to the resistor cascade between the cascade input
105
and the ground connection
106
such that the reference voltage U
ref
drops in partial voltages between the resistors
102
. These partial voltages are evaluated by a respective one of the comparators
103
. To make illustration clearer,
FIG. 1
shows just three comparators
103
, but the flash ADC can have any number of comparators
103
.
An analog signal to be converted, i.e. an analog voltage U
a
, is applied via an analog signal input
107
to a second input
108
on all the comparators
103
in parallel. The comparators
103
then compare the analog voltage U
a
applied to the second input
108
with the respective partial voltage applied to the first input
104
. If the analog voltage U
a
applied to one of the comparators
103
is higher than the partial voltage applied, then the comparator
103
has been activated and outputs at an output
109
a bit signal which corresponds to a first bit value “1”, otherwise the bit signal corresponds to a second bit value “0”.
Finally, a digital evaluation unit
110
produces a digital output signal D in line with the comparator
103
activated with the highest partial voltage, and outputs this signal at a digital signal output
111
.
FIG. 1
shows, in each of the comparators
103
, a graph
112
plotting a probability density dW against a voltage difference &Dgr;U. In this case, dW denotes the probability density of there being a change from a first bit value “1” to a second bit value “0” or vice versa for the indicated input difference voltage &Dgr;U at the output
109
of the respective comparator
103
. An ideal comparator has an infinitesimally narrow probability density dW, i.e. the change from one bit value to the other bit value takes place exactly at the input difference voltage &Dgr;U=0. On account of statistical effects, real comparators have a broad probability density dW, however. By way of example, the result of this is that the comparator
103
would (not) be activated even though an analog voltage U
a
which is (higher) lower than the applied partial voltage is applied. The voltage difference &Dgr;U plotted in the graph
112
is formed from the applied partial voltage of the reference voltage U
ref
and the applied analog voltage U
a
.
FIG. 2
shows a graph
201
plotting a curve
202
for the response probability density
203
of comparators
103
in the flash ADC described in
FIG. 1
against the applied analog voltage U
a
204
. The graph
201
results from a combination of the individual probability densities dW of the comparators
103
, which are shown in
FIG. 1
as individual graphs
112
in the comparators
103
.
Since each comparator
103
is associated with a different portion of the reference voltage U
ref
, the curve
202
for the response probability density
203
of the comparators
103
is obtained from a linear plot of the individual probability densities dW of adjacent comparators
103
in a rising direction against the applied analog voltage U
a
204
. The result of the virtually isolated probability densities dW of the individual comparators
103
is that the changes in the comparators
103
are very precisely defined and the flash ADC thus has a high level of accuracy. On the basis of the prior art, flash ADCs are produced with accuracies of typically 5 to 6 bits and are used, inter alia, in the read paths of hard disks.
A commonly used analog/digital converter normally involves the use of resistors for producing the reference values, which are produced on the semiconductor substrate from a semiconductor material, each corresponding resistance value being determined by the number of atomic, molecular and crystallite boundaries in the semiconductor material within the respective resistance area A.
If the resistance area A is reduced, the atomic, molecular or crystallite number in the semiconductor crystal falls, and hence the number of atomic, molecular and crystallite boundaries falls, as a result of which the standard deviation of the resistance value corresponding to this resistance area A increases by the factor ({square root over (A)})
−1
. If the resistance area A decreases, the probability W that a comparator has been activated and outputs an incorrect bit signal, even though an analog voltage U
a
is applied which is lower than the reference network's nominal partial voltage applied to the comparator in question, thus increases.
The accuracy of such an analog/digital converter is also determined by the statistical fluctuations in the transistor parameters. By way of example, the variation in the threshold voltage of an MOS transistor likewise decreases by a factor of ({square root over (A)})
−1
as the area of the transistor increases. This parameter variation in the comparator's transistors results in the “input offset voltage”, so that a comparator does not turn round at an input voltage difference &Dgr;U of exactly &Dgr;U=0, but rather at an input voltage difference &Dgr;U which corresponds to the individual comparator offset.
These statistical variations limit the linearity of the overall analog/digital converter system, which is why the design needs to take into account sufficient component areas in order to satisfy the demands on accuracy.
If the individual comparators have sufficient accuracy, then a chain of comparators connected to a resistor network in the manner described above has an output signal which is known as a thermometer code. This means that all the comparators whose first input is connected to a partial voltage of the reference voltage U
ref
which is lower than the analog voltage U
a
applied to the second input output the bit value “1”, whereas all the other comparators output the bit value “0”. Such output signals can then be converted particularly easily into a digital output word. Normally, a thermometer binary coder and the outputs of the comparators also have a correction logic unit connected between them, said correction logic unit eliminating so called “bubbles” in the thermometer code (a “0” between a plurality of “1”s and vice versa) in order to permit reliable binary coding.
The resistor network described above in connection with the flash ADCs is used for providing reference partial voltages with which an analog input voltage U
a
is compared in the comparators. Alternatively to the resistor networks, any other reference signal network can also be used. Thus, by way of example, it is also possible to use current sources having different output currents as a reference signal. The information-bearing variable used can thus be not just voltages, but rather “current-mode” solutions are also possible, which involve the information being represented by currents.
In contrast to the parameter variations, the parasitic capacitances which arise for relatively large component areas and are generally unwanted increase as the component area A increases. As a result, the signal processing speed decreases, however. This therefore means that a high level of accuracy in a commonly used analog/digital converter is to the detriment of the
Altera Law Group LLC
Infineon - Technologies AG
Mai Lam T.
Stone Jeffrey R.
Tokar Michael
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