Analog to digital converter

Details Analog to digital converter Analog to digital converter

2002-07-22

2003-12-23

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

Reexamination Certificate

active

06667706

ABSTRACT:

The subject invention relates to an analog to digital converter, computing all the bits in parallel and simultaneously without using any decoding logic.
The object of the subject application is to develop a system to be applied on different kinds of implementations offering different degrees of tradeoff between speed and hardware requirement.
BACKGROUND OF THE INVENTION
Signals in the real world are real-valued, or analog in nature, as the output of a pressure or temperature sensor, the amplitude of a speech signal, etc. For example, the output voltage of a microphone may be 2 millivolts (mV) in response to a certain acoustic signal. Suppose that the output of the microphone ranges from a minimum of 0 mV to a maximum of 8 mV. The output of the microphone under consideration may typically be processed by some form of signal processing system.
Most processing equipment today are digital in nature, and they work with signals which are binary valued. In a digital or binary representation, a signal is represented by a word, which is composed of a finite number of bits.
The number of bits is termed as the word length, henceforth denoted by N. Since each bit in the word is either a 0 or a 1, the number of possible combinations is finite. The maximum number of possible binary numbers with N bits is equal to 2
N
. Since an infinite number of real values exist in a given analog range, the binary or digital representation is necessarily an approximate one.
If the output of the microphone can be represented by 3 bits, these bits are denoted by V
1
, V
2
and V
3
. The number represented by the 3 bits (in millivolts) is given by V
1
+2V
2
+4V
3
. In general, with N bits, the digital representation is equal to
∑
i
=
1
N
⁢
2
i
-
1
·
V
i
where the significance of V
N
is the highest (it is weighted by 2
N−1
; this bit is termed as the Most Significant Bit (MSB). Conversely, V
1
is termed as the Least Significant Bit (LSB).
The problem of analog-to-digital conversion is that of finding an N-bit binary word which best approximates a given analog value x, where N is an integer. An Analog to Digital Converter (ADC) for N bits has N output bits labeled V
1
to V
N
, where each V
i
, (i=1,2, . . . N) is either 0 or 1. Given an analog input whose value is denoted by a number x, the ADC is required to determine the values of V
1
to V
N
such that the error
&LeftBracketingBar;
x
-
∑
i
=
1
N
⁢
2
i
-
1
·
V
i
&RightBracketingBar;
is minimized. If N is chosen to be 3, then the following table gives the outputs of a 3-bit ADC for different values of x. The values of x are assumed to lie within the range 0 to 8.
X
V
3
V
2
V
1
x
V
3
V
2
V
1
x
V
3
V
2
V
1
X
V
3
V
2
V
1
0
000
1
001
1.25
001
1.4
001
1.7
010
2
010
2.2
010
2.4
010
3
011
3.1
011
4
100
4.4
100
4.9
101
5
101
6
110
6.3
110
6.6
110
7.2
111
7.7
111
8.0
111
The existing methods of ADC as known conventionally include flash converters, dual-slope, ramp, sigma-delta, successive approximation, etc.
Presently, flash converters are the only known way of obtaining all the output bits in parallel. A N-bit flash converter requires of the order of 2
N
comparators. Let the input signal range from 0 to R. The range from 0 to R is divided into 2
N
levels. These comparators each output a 1 or 0 depending on whether the analog input x exceeds or is below the corresponding level. Decoding logic uses these 2
N
variables to generate the N output bits. The decoding logic is made up of gates. Practical considerations limit the number of inputs (fan-in) and fan-out of each gate. As a result, the delay due to decoding logic increases as O(N log
2
N) or faster. These considerations limit the word length of a flash converter.
Since all the bits of a flash converter are obtained simultaneously, the time required to generate the output bits once the analog input has been presented is small.
In the case of a flash converter, the hardware grows exponentially with the number of bits; the number of comparators required for a N-bit converter is 2
N
and additional decoding logic is required.
Improved systems based on the flash converter use fewer comparators, where the number of comparators required can be written as 2
KN
, where K is a fraction between 0 and 1. In other words, the rate at which hardware requirements increase still remains an exponential function of N.
Other conventional approaches such as dual-slope and successive approximation methods require considerably less hardware. However, in these methods, the bits cannot be computed in parallel. As a result, the time taken to generate the binary approximation, which is termed as the conversion time, is much higher than for a flash Analog to Digital Converter.
The conversion time is closely related to the sampling rate that can be handled by the Analog to Digital Converter. This is the rate at which input samples can be accepted. Obviously, the next sample cannot be taken up by the ADC until the previous one has been converted.
In an other conventional frequency domain approach called sigma-delta conversion, the input signal is sampled at a high rate to achieve an analog to digital conversion. The scheme requires the extensive use of filters and additional hardware. An additional drawback is the need for the circuitry to work at a high speed, typically much higher than the sampling rate. This also creates hurdles with regard to hardware or circuit realization of such methods.
PRIOR ART
One approach to reducing the circuitry is known as a folding/interpolating type converter. As prior art of such a folding-interpolating ADC (FADC), there is, for example, that which is disclosed as U.S. Pat. No. 6,236,348 B1. In a folding/interpolating ADC, the input analog signal is converted into a set of n1 higher order bits and n2 lower order bits, where n1+n2=N. The idea in such a converter is to divide the range of the signal into segments. The higher order bits are obtained by determining the segment in which the value of a given input sample lies, while the n2 lower order bits are obtained by using 2
n2
comparators and a suitable encoder.
Mandl, in patent U.S. Pat. No. 5,659,315, teaches us a method of accomplishing oversampled sigma-delta analog to digital conversion. The sampled analog signal is first converted using a ADC with a lower resolution. The conversion error is determined by obtaining the difference between the value of the digital word and the input sample. The error is fed to an integrator and again converted by using the ADC with a smaller resolution. In this manner, in succcessive steps, the quantization error reduces. In the limit, the smaller resolution ADC can be thought of as a one-bit ADC, which is no more than a comparator. Such a comparator compares a given input with a reference signal and outputs a “1” if the input exceeds the reference, and outputs a “0” if the input is less than the reference signal.
A variety of designs based on delta modulation have also been reported. Bader, in patent U.S. Pat. No. 4,291,300, teaches us a method of converting a time-varying (AC) signal which is superimposed on a larger, fixed (DC) component. It is concerned with tracking the time-varying part of the signal and its conversion, which is accomplished by means of a capacitive storage and by incremental variation of a reference signal. The variation of the reference signal is achieved by a series of clock pulses.
Another approach known as an Algorithmic ADC or cyclic ADC employs a very different approach. Kerth, in patent U.S. Pat. No. 5,644,308, discloses a design of an Algorithmic ADC. In an Algorithmic ADC, the conversion is carried out in a sequential manner, by employing the conventional restoring numerical division principle. The input signal sample is multiplied by two and the product is then compared with a reference. If the product exceeds the reference, then the output bit is set to “1” and the reference is subtracted from the product. Otherwise, the output bit is set to “0” and no subtraction is carried out. The remaining part of the produ

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