Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2000-08-10
2002-02-12
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S127000, C341S155000, C341S158000, C341S159000
Reexamination Certificate
active
06346902
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an analog to digital converter comprising a resistive reference ladder with a plurality of pairs of taps for generating a plurality of pairs of reference voltages and means for sensing a differential input signal at each of said plurality of pairs of reference voltages. An analog to digital converter of this kind is known from an article “A 10-b, 100 MS/s CMOS A/D Converter” of K. Y. Kim et al in IEEE Journal of Solid State Circuits, Vol. 32, No. 3, March 1997.
In present day integration technics with its very small dimensions and low voltages, it is difficult to make an a/d converter with a sufficiently clean (distortion free) ground potential for the reference voltage and for the input voltage. Therefore it has become common practice to use a differential input arrangement for the signal voltage and the reference voltage, so that any common mode distortions are balanced out. Another advantage of a differential input arrangement is that the voltage span of the input signal can be nearly twice the voltage span in case a single ended input arrangement is used.
A prior art implementation of a differential input a/d converter, which is e.g. applied in applicant's integrated circuit TDA 8085, has two so called dynamic reference ladders, which generate the differential reference voltages and which simultaneously carry the partial voltages of the differential input signal. This a/d converter has relatively few comparators, because it directly compares the sum of one partial input voltage and one reference voltage with the sum of the other partial input voltage and the other reference voltage. Another advantage is that common mode voltages are automatically cancelled out. However, the reference ladders, together with the input capacitances of the comparators, act as a low pass filter for the input signal, so that this type of a/d converter is not suitable for converting wideband signals. Moreover, the summing up of the reference voltage and input voltage substantially reduces the maximum voltage span of the input voltage.
In contradistinction, the a/d converter described in the above referenced article, uses a static reference ladder, which need more comparators but which has better high frequency performance than the one with dynamic ladders. However the number of taps on the reference ladder still presents a problem to be encountered. In a full flash a/d converter with a single ended input and generating e.g. an 8-bit encoded digital representation of the analog input signal, the signal is quantized into 256 levels requiring a reference ladder with 255 taps. The differential implementation of the quantizer further increases the number of reference taps by a factor 2. There are already proposed methods to substantially reduce the number of reference taps and the number of comparators. A well known technic is to use a flash quantizer only for the most significant bits, and generating folding signals and quantizing these folding signals for obtaining the less significant bits. The number of comparators and the number of taps may further be reduced by generating only a few folding signals and obtaining the other folding signals by linear interpolation. With these technics an 8-bit differential quantizer may in practice require a reference ladder of not more than 38 taps.
SUMMARY OF THE INVENTION
The present invention seeks to provide a further reduction of the number of reference taps in a differential quantizer with a static reference ladder and the analog to digital converter of the present invention is therefore characterized in that each of said plurality of pairs of taps of the reference ladder, which is used to sense a certain level of the differential input signal, is also used to sense the differential input signal at the level which is reversed in polarity with respect to said certain level. The invention allows in an a/d converter the use of a differential input arrangement with no more (e.g. 19) reference taps than are normally required in an a/d converter with a single ended input arrangement.
Apart from the reduction in reference taps, the a/d converter of the present invention has the advantage that, for the same magnitude of the differential input signal to be sensed, the total voltage across the reference ladder is half the voltage across the reference ladder of the above referenced article of K. Y. Kim et al. Therefore, the a/d converter of the present invention can be implemented in an integrated circuit chip which need only half the supply voltage of the integrated circuit in which the prior art converter is implemented. Furthermore, in prior art a/d converters there is undesired crosstalk from the input signal to the reference ladder through the input capacitances of the sensing means. In contradistinction, in the a/d converter of the present invention, the crosstalk caused by the two polarity reversed input signals through the input capacitances of the respective sensing means connected to the same tap, cancel against each other, so hat the reference voltages at the taps of the ladder remain substantially free of input signal residues.
It is a further object of the present invention to provide an analog to digital converter which is characterized in that each of said means for sensing the differential input signal comprises a pair of transconductance amplifiers, which receives the differential input signal and a pair of reference voltages, and means to combine the output currents of the transconductance amplifiers. By this measure a simple and efficient way to combine the outputs of the amplifiers into a single differential output current is obtained.
In a differential a/d converter using a static reference ladder it is of importance that the common mode voltage of the reference ladder equals the common mode voltage of the differential input voltage. In the above mentioned prior art publication the differential input voltage and the differential reference ladder are both assumed to be balanced at zero ground level. In integrated circuit technic this will usually not be the case and to cope with this problem the analog to digital converter of the present invention may further be characterised by means to equalize the common mode voltage of the differential input signal and the midtap voltage of the reference ladder with each other.
REFERENCES:
patent: 5119094 (1992-06-01), Brokaw
patent: 5528242 (1996-06-01), Kumar
patent: 5877718 (1999-03-01), Andoh et al.
patent: 6002356 (1999-12-01), Cooper
“A 10-b, 100-MS/s CMOS A/D Converter”, by Kwang Young Kim et al, IEEE Journal of Solid-State Circuits, vol. 32, No. 3, Mar. 1997.
Van De Plassche Rudy Johan
Venes Arnoldus Gerardus Wilhelmus
Mai Lam T.
Tokar Michael
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