Analog to digital converter

Details Analog to digital converter Analog to digital converter

1998-05-11

2001-08-28

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S172000, C341S155000, C341S150000, C327S075000

Reexamination Certificate

active

06281831

ABSTRACT:

DETAILED DESCRIPTION OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog to digital converter for converting an analog voltage signal into a digital voltage signal by a voltage driven type circuit.
2. Prior Art
An analog to digital converter (AID converter) is widely used having a voltage-divider consisting of serial resistors. Such A/D converter consumes a lot of electrical power because current flows constantly through the resistor.
The inventors of the present invention have proposed an A/D converter in Patent Publication Hei09-083364, in which a plurality of thresholding circuits corresponding to a plurality of bits of a digital output voltage. The thresholding circuits are parallelly connected to an analog input voltage. An output of one thresholding circuit is input to thresholding circuits of lower bits with weighted by predetermined weight. High accuracy and low electric power consumption is realized.
FIG. 15
shows an example of four bits output of the A/D converter (quantizing circuit) above. However, the A/D converter is applicable to more number of bits. There are provided four threshold circuits Th
3
to Th
0
of four level thresholds corresponding to the output bits. Each of the thresholding circuits Th
3
to Th
0
has a capacitive coupling with a plurality of capacitances and four stages MOS inverters INVi
1
to INVi
4
(i=0 to 3). The first stage MOS inverter INVi
1
(i=0 to 3) is of a threshold voltage Vdd/2 when a supply voltage is Vdd. INVi
1
outputs Vdd when an input voltage is less than the threshold and the ground voltage GND (0) when the input is more than the threshold.
There is also a successive comparison type A/D converter having a sampling and holding circuit a comparator and a D/A converter. The error depends on the offset voltage of the sampling and holding circuit and of the comparator, and mainly on the performance of the D/A converter. The linearity is deteriorated by the D/A converter. Further, lower electrical power consumption, higher gain and higher stability are requested.
The first stage MOS inverter is for detecting whether the output of the capacitive coupling exceeds the predetermined threshold or not and the second stage MOS inverter inverts the output of the first stage MOS inverter. The third MOS increases inverting speed and the fourth inverts the output of the third MOS inverter.
The thresholding circuits generate output voltages Vb
3
to Vb
0
, respectively, and intermediate outputs Vb
3
′ to Vb
0
′ are generated by the third inverters INVi
3
, respectively. AIN is an analog voltage input terminal, Vdd is the supply voltage and GND is the ground voltage.
The thresholding circuit Th
3
of the third bit has a capacitive coupling consisting of capacitances C
31
, C
32
and C
33
for weighting the input voltages, respectively. Four stages serial MOS inverters INV
31
to INV
34
is connected at the first stage to an output of the capacitve coupling. An analog input voltage Vin is input from the input terminal AIN of the input capacitance C
31
, the supply voltage Vdd is input to the input capacitance C
32
and the ground voltage GND is input to the input capacitance C
33
. These voltages are weighted by predetermined weights and added together, as mentioned below.
The thresholding circuit Th
2
of the second bit has a capacitive coupling consisting of capacitances C
21
, C
22
, C
23
and C
24
for weighting the input voltages, respectively. Four stages serial MOS inverters INV
21
to INV
24
is connected at the first stage to an output of the capacitve coupling. An analog input voltage Vin is input to the input capacitance C
21
, the supply voltage Vdd is input to the input capacitance C
22
, the ground voltage GND is input to the input capacitance C
23
and the output Vb
3
′ is input to the input capacitance C
24
from the third stage inverter INV
33
of the thresholding circuit Th
3
.
The thresholding circuit Th
1
of the first bit has a capacitive coupling consisting of capacitances C
11
, C
12
, C
13
, C
14
and C
15
for weighting the input voltages, respectively. Four stages serial MOS inverters INV
11
to INV
14
is connected at the first stage to an output of the capacitive coupling. An analog input voltage Vin is input to the input capacitance C
11
, the supply voltage Vdd is input to the input capacitance C
12
, the ground voltage GND is input to the input capacitance C
13
, the output Vb
3
′ is input to the input capacitance C
14
from the third stage inverter INV
33
of the thresholding circuit Th
3
and the output Vb
2
′ of the thresholding circuit Th
2
is input to the input capacitance C
15
.
The thresholding circuit Th
0
of the LSB has a capacitive coupling consisting of capacitances C
01
, C
02
, C
03
, C
04
, C
05
and C
06
for weighting the input voltages, respectively. Four stages serial MOS inverters INV
01
to INV
04
is connected at the first stage to an output of the capacitive coupling. An analog input voltage Vin is input to the input capacitance C
01
, the supply voltage Vdd is input to the input capacitance C
02
, the ground voltage GND is input to the input capacitance C
03
, the output Vb
3
′ is input to the input capacitance C
06
from the third stage inverter INV
33
of the thresholding circuit Th
3
, the output Vb
2
′ is input to the input capacitance C
05
from the third inverter INV
23
of the thresholding circuit Th
2
and the output Vb
1
′ is input to the input capacitance C
04
from the third inverter INV
13
of the thresholding circuit Th
1
.
The capacity ratio of the capacitances C
31
to C
33
, C
21
to C
24
, C
11
to C
15
and C
01
to C
06
are shown in the table of FIG.
16
. Here, Cu is a unit capacity.
As for the thresholding circuit Th
0
for the LSB, the capacities for the supply voltage and the ground voltage are “1”, the capacity for the intermediate output Vb
1
′ of the higher thresholding circuit Th
1
by one bit is “2”, the capacity for the intermediate output Vb
2
′ of the higher thresholding circuit Th
2
by two bits is “4”(=2
2
), the capacity for the intermediate output Vb
3
′ of the higher thresholding circuit Th
3
by three bits is “8”(=2
3
) and the capacity for the analog input voltage Vin is “16”(=2
4
).
As mentioned above, the intermediate outputs from the upper threshold circuits and the analog input voltage Vin are weighted by a power of “2” and added together by the weighting circuit.
In
FIG. 17
, an output of a capacitive coupling is shown.
FIG. 17
shows an example of a capacitive coupling consisting of input capacitances C
1
to C
5
. Assuming that the total electric charge in the input capacitances is zero in the initial condition, the total electric charge is constant to be zero from a reference point of an output terminal when the input voltages are connected the input capacitances. The following formula (1) is given. Here, Vo is an output voltage of the output terminal.
C
1
(
V
1
−
Vo
)+
C
2
(
V
2
−
Vo
)+
C
3
(
V
3
−
Vo
)+
C
4
(
V
4
−
Vo
)+
C
5
(
V
5
−
Vo
)=0  (1)
Then, Vo is given by the formula (2).
Vo
=
∑
i
=
1
5
⁢
 
⁢
CiVi
∑
i
=
1
5
⁢
 
⁢
Ci
(
2
)
Therefore, the output of the capacitive coupling is a total summation of the input voltages weighted by the capacities of the input capacitances.
The thresholding circuit Th
3
has capacity ratio of the input capacitances C
31
to C
33
is C
31
:C
32
:C
33
=16:8:8. The output voltage V
3
is as in the formula (3).
V3
=
1
2
⁢
Vin
+
1
4
⁢
Vdd
(
3
)
When the analog input voltage Vin=Vdd/2, V
3
is equal to the threshold voltage Vth(=Vdd/2) of the inverter circuit INV
31
. When 0≦Vin<Vdd/2, the output of the inverter INV
31
, that is, the intermediate output Vb
3
′ of the MOS inverter INV
31
is Vdd and the output of the output Vb
3
is zero. When Vdd/2≦Vin<Vdd, the output of the inverter INV
31
is inverted, the intermediate output Vb
3
&p

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