Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Patent
1996-09-16
1998-03-24
Young, Brian K.
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
341155, H03M 136
Patent
active
057317763
ABSTRACT:
A ladder resistance (1) consisting of resistance elements (r1, r2, . . . , r8) connected in series with intermediate taps (T1, T2, . . . , T7) interposed is so arranged as to be folded back at its midpoint. Pairs of differential comparators (C1 and C7, C2 and C6, . . . ) which are connected to common intermediate taps are each disposed adjacently so as to be nearest to the intermediate tap to be connected thereto. Accordingly, wires connecting the differential comparators (C1, C2, . . . , C7) to the intermediate taps (T1, T2, . . . , T7) become shorter and an area of a semiconductor chip needed for arranging the wires can be reduced. Thus, reduction in area of the semiconductor chip needed for providing the device therein is achieved.
REFERENCES:
patent: 5554989 (1996-09-01), Kumamoto et al.
IEEE Journal of Solid-State Circuits, vol. 29, No. 4, pp. 516-522, Apr. 4, 1994, T. Miki, et al., "A 10-b 50 MS/s 500-mW A/D Converter Using a Differential-Voltage Subconverter".
Kumamoto Toshio
Matsumoto Osamu
Mitsubishi Denki & Kabushiki Kaisha
Young Brian K.
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