Analog-to-digital converter

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C134S156000

Reexamination Certificate

active

11363968

ABSTRACT:
Included are a first unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the first analog signal, a second unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the second analog signal, a first switch connecting the first unit to an output side of the second unit, a comparator comparing a differential value between the first analog signal and the second analog signal with a differential value between the comparison signal of the first DAC and an output signal of the second DAC, and an electric potential control circuit controlling fluctuations in electric potentials of the first analog terminal and the second analog terminal.

REFERENCES:
patent: 4803462 (1989-02-01), Hester et al.
patent: 4831381 (1989-05-01), Hester
patent: 4989002 (1991-01-01), Tan
patent: 5581252 (1996-12-01), Thomas
patent: 6714151 (2004-03-01), Tachibana et al.
patent: 6750800 (2004-06-01), Yoshinaga
patent: 6753801 (2004-06-01), Rossi
patent: 6909391 (2005-06-01), Rossi
patent: 06-164399 (1994-06-01), None
patent: 11-017543 (1999-01-01), None
patent: 2000-201077 (2000-07-01), None
R.K. Hester, et al., “Fully Differential ADC with Rail-to-Rail Common-Mode Range and Nonlinear Capacitor Compensation”, IEEE Journal of Solid-State Circuits; vol. 25; No. 1; Feb. 1990, pp. 173-183.
Gilbert Promitzer, “12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s”, IEEE Journal of Solid-State Circuits, Jul. 2001, pp. 1138-1143.

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