Analog-to-digital converter

Details Analog-to-digital converter Analog-to-digital converter

2004-03-23

2004-12-28

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S158000, C341S159000

Reexamination Certificate

active

06836237

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) converter, and more particularly, to a serial-parallel A/D converter suitable for use with realization of an integrated circuit.
2. Description of the Related Art
Comparing to the case of a parallel A/D converter whose circuit scale is increased exponentially in accordance with the number of bits, the circuit configuration of a serial-parallel A/D converter can be simplified, and the serial-parallel A/D converter is more suitable for an integrated circuit fabrication.
In the serial-parallel A/D converter such as shown in
FIG. 3
, when four-bits resolution is adopted for example, three comparators
1
in use of the high bits compares an input voltage Vin with each of the partial voltages of a reference voltage V
REF
, being divided by resistances, to determine the higher two bits D
U
by way of an encoding circuit
2
. Further, a certain switch is selected from a group of switches 3 to 6 on the basis of the result of determination so as to compare the input voltage with each of the selected reference partial voltages by three comparators
7
in use of the low bits, by activating said selected switch. Thus, two lower bits D
L
are determined by way of an encoding circuit
8
.
In general, an A/D converter for 2n bits determines higher “n” bits through use of 2
n
−1 comparators, and lower “n” bits through use of other 2
n
−1 comparators. Therefore, a required number of comparators is 2
n+1
−2. When compared with the number of comparators required by a complete parallel A/D converter; that is, 2
2n
−1, the required number of comparators can be considerably reduced.
The serial-parallel A/D converter employs different groups of comparators to determine high-bit data and low-bit data and causes the comparators to perform comparing operations at different timings. Hence, an operational error (a mismatch) due to a difference in circuit configurations or the like may happen in comparing operations in-between.
In order to prevent occurrence of such a operational error in comparing operations, such as can be seen during conversion of high bits and low bits, the following practice is known to be adopted such as disclosed in Japanese patent publication Hei 06-81048. That is, in a case where 2n bits are subjected to A/D conversion and if the high bits are given as “n” bits (e.g., two bits) at the time of A/D conversion of 2n bits (e.g., four bits), the numbers of the comparators to be used for converting the low bits are increased (e.g., from three comparators to seven comparators) so that the range of reference partial voltages to be compared is vertically expanded with giving the low bits as n+1 bits (e.g., three bits). In this way, the operational error can be compensated.
In said low-bit comparator, since an error range allowed for determining a least significant bit (LSB) becomes narrow, the low-bit comparator must be structured more accurately than that of the high-bit comparator. Consequently, the amount of electric current consumption by the comparator becomes larger, and a large area is also required even if many efforts were made in a circuit design.
As mentioned above, in order to prevent occurrence of a operational error in comparing operation during conversion of high and low bits, the conventional serial-parallel A/D converter shall be provided with the additional high-precision low-bit comparators. Therefore, there arises a problem of an increase in the amount of electric current consumption by the serial-parallel A/D converter itself as well as a problem of increase in the required area for the IC chip.
SUMMARY OF THE INVENTION
Accordingly, the present invention aims for providing an analog-to-digital converter which performs serial-parallel operations in two steps to carry out A/D conversion so as to prevent occurrence of a operational error in comparing operations during conversion of high and low bits with lowering the amount of electric current consumption without increasing the number of the low-bit comparators which requires high-precision to be made.
According to the first aspect in this invention, an analog-to-digital converter for converting an input voltage into a plurality of digital signals through serial-parallel conversion is provided such that each of said plurality of digital signals is comprised of N bits data where N is an integer of not less than two, the converter comprising: a partial voltage generation circuit which generates a plurality of partial voltages for said N bits by means of dividing a reference voltage; high-bits side comparators for comparing said input voltage with each partial voltage, said each partial voltage being in a part of said plurality of partial voltages, which becomes data of high bits whose bit number is more than half of the N bits; a high-bits side encoding circuit which encodes comparison results from said high-order comparators and outputs said encoded comparison results as high-bit data having said bit number of said high bits ; selection circuits for selecting a part of said partial voltages, which becomes data of low bits with a bit number being defined as half of the plurality of said N bits, in accordance with said comparison results of said high-bits side comparators;
low-bits side comparators for comparing each partial voltage of said partial voltages selected by said selection circuits with said input voltage; a low-bits side encoding circuit which encodes comparison outputs from said low-bits side comparators and outputs said encoded comparison results as low-bit data having said bit number of said low bits; and a logic circuit which outputs N bits data based on a matching being made between the high-bit data and the low-bit data, wherein when said matching stands between the high-bit data and the low-bit data, said N bits data is output in accordance with predetermined conditions, while when said matching does not stands in-between, said high-bit data is modified according to said low-bit data,
and said N bits data is output in accordance with predetermined conditions.
According to the second aspect in this invention, it is characterized by said analog-to-digital converter where the N bits is defined by 2n bits, the high-bit data by n+1 bits, and the low-bit data by “n” bits.
According to the third aspect in this invention, it is characterized by the analog-to-digital converter, further comprising: a sample-and-hold circuit which samples and holds an input signal from the outside every sampling cycle to generate said input voltage; high-bits side latch circuits which latch comparison outputs from said high-bits side comparators and input said latched comparison outputs to said high-bits side encoding circuit; and low-bits side latch circuits which latch comparison outputs from said low-bits side comparators and input said latched comparison outputs to said low-bits side encoding circuit, wherein said high-bits side latch circuits and said low-bits side latch circuits perform latching operations at different timing within the same cycle of said sampling cycle.


REFERENCES:
patent: 4745393 (1988-05-01), Tsukada et al.
patent: 5099240 (1992-03-01), Nakatani et al.
patent: 5194866 (1993-03-01), Imaizumi et al.
patent: 5534864 (1996-07-01), Ono et al.
patent: 5923277 (1999-07-01), Takeda
patent: 6014097 (2000-01-01), Brandt
patent: 6-81048 (1994-10-01), None

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