Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-10-04
2004-04-06
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S162000, C341S163000
Reexamination Certificate
active
06717542
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an analog to digital converter (A-D converter) for converting an analog signal into a digital signal. More particularly, the present invention relates to a successive approximation type A-D converter for successively comparing an analog input voltage with a comparison reference voltage on a bit-by-bit basis from the most significant bit of a digital signal.
2. Description of the Background Art
A-D converters for converting an analog signal into a digital signal are widely used in a variety of fields. Since a signal is digitally processed, high-speed, accurate signal processing can be implemented while reducing the influences such as noises. Moreover, the use of digital circuitry as processing circuitry stabilizes circuit operation and simplifies the circuit structure as much as possible.
Various circuit structures are used for such an A-D converter. A successive approximation method is conventionally known as an A-D conversion method used in the A-D converter. In this method, the bit values of the digital signal are determined by successively comparing an analog input signal with a comparison reference voltage on a bit-by-bit basis from the most significant bit. The comparison reference voltage level for the next bit value is determined according to the comparison result of the upper bit. The variation amount of the comparison reference voltage is predetermined for each comparison step. The variation amount corresponding to the weight of each respective bit of the digital signal is normally used as the variation amount of the comparison reference voltage.
FIG. 26
schematically shows an example of the structure of a conventional A-D converter. Referring to
FIG. 26
, the conventional A-D converter includes a ladder resistor
1
for generating a comparison reference voltage candidates through resistance division, a selector
2
for selecting an output voltage of the ladder resistor
1
in accordance with a control signal from a control circuit
100
to produce a comparison reference voltage for each comparison, a sample-and-hold circuit (S/H circuit)
3
operating under the control of control circuit
100
for sampling and holding an analog input signal (voltage) Vin, a comparator
4
for comparing the voltage held by the S/H circuit
3
with the comparison reference voltage selected by the selector
2
, and a register
110
for storing an output signal of the comparator
4
successively. Register
110
outputs an n-bit digital signal D.
Control circuit
100
determines various operation timings according to a clock signal CLK from a clock generator
10
, and generates a selection control signal to selector
2
according to a bit value stored in register
110
. Clock generator
10
generates a basic internal clock signal CLK for determining each comparison cycle in accordance with an external clock signal. A digital conversion cycle for each analog input signal and a comparison/determination cycle for each bit value of each digital signal are determined based on this internal clock signal CLK.
Ladder resistor
1
resistance-divides externally generated or internally generated reference voltages VRT and VRB to generate candidate comparison reference voltages. The maximum output voltage value of ladder resistor
1
is a reference voltage VRT−0.5LSB, and the minimum output voltage value thereof is a reference voltage VRB+LSB. Voltage LSB represents a resolution of A-D conversion, and corresponds to a voltage of the least significant bit of the digital signal. Provided that the digital signal is an N-bit signal, voltage LSB is given by (VRT−VRB)/2{circumflex over ( )}N, where the symbol “{circumflex over ( )}” denotes power.
FIG. 27
illustrates an example of the comparison sequence of the A-D converter shown in FIG.
26
. It is herein assumed that the analog input voltage is converted into a 5-bit digital signal. The abscissa indicates time and the ordinate indicates voltage. Five conversion cycles are shown in FIG.
27
. Ladder resistor
1
resistance-divides voltages the VRT and VRB and generates voltages in the range of 30.5LSB to 0.5LSB in steps of 1LSB as candidate comparison reference voltages.
In order to generate a 5-bit digital signal, ladder resistor
1
generates the voltage levels of thirty steps in accordance with the voltages VRT and VRB. Since the digital signal is a 5-bit signal, the unit variation amount (increment) of the comparison reference voltage, LSB, is given by (VRT−VRB)/2{circumflex over ( )}5. The minimum output voltage of ladder resistor
1
is a voltage VRB+0.5LSB, and the maximum output voltage thereof is a voltage VRB+30.5LSB. When analog input voltage Vin is higher than voltage VRB+30.5LSB, every bit of the resultant 5-bit digital signal is “1”. On the other hand, when analog input voltage Vin is lower than voltage VRB+0.5LSB, every bit of the resultant digital signal is “0”.
In the successive approximation method, each bit value of the digital signal is sequentially determined on a bit-by-bit basis from the most significant bit based on comparison between an analog input voltage and a comparison reference voltage. Therefore, comparison must be performed five times in order to generate a 5-bit digital signal.
Now, conversion operation into a 5-bit digital signal of the A-D converter shown in
FIG. 26
will be described with reference to FIG.
27
.
Referring to
FIG. 27
, it is now assumed that analog input voltage Vin is at a voltage level VRB+10LSB. S/H circuit
3
shown in
FIG. 26
samples and holds this analog input voltage Vin.
In the first comparison, selector
2
selects a median of the candidate voltages output from ladder resistor
1
, that is, VRB+15.5LSB, as a comparison reference voltage VC. Comparator
4
then compares analog input voltage Vin held in S/H circuit
3
with the selected comparison reference voltage VC. In the first comparison, analog input voltage Vin is lower than the comparison reference voltage. Therefore, comparator
4
outputs “0” and register
110
stores bit “0”. The first comparison result corresponds to the fifth bit (most significant bit) of the final conversion result, that is, the digital signal.
Control circuit
100
generates a control signal to selector
2
according to the value of the fifth bit (most significant bit) stored in register
110
or the output signal of comparator
4
. Since comparator
4
outputs “0” in this stage, selector
2
selects a voltage lower than the comparison reference voltage of the first comparison by 8LSB as a comparison reference voltage of the second comparison. More specifically, in the second comparison, comparison reference voltage VRB+7.5LSB is selected and applied to comparator
4
. In the second comparison, analog input voltage Vin is higher than comparison reference voltage VRB+7.5LSB. Therefore, comparator
4
outputs “1” and register
110
stores bit “1” as a value of the fourth bit.
According to the output signal of comparator
4
or the bit value stored in register
110
, control circuit
100
generates such a selection control signal causing selector
2
to select a voltage higher than the comparison reference voltage of the second comparison by 4LSB, that is, VRB+11.5LSB, as a comparison reference voltage of the third comparison. In the third comparison, analog input voltage Vin is lower than the selected comparison reference voltage. Therefore, comparator
4
outputs “0” and register
110
stores the output signal (bit value) of comparator
4
at the position of the third bit.
According to the third comparison result, control circuit
100
generates a selection control signal such that selector
2
selects a voltage lower than the comparison reference voltage of the third comparison by 2LSB, that is, VRB+9.5LSB, as a comparison reference voltage of the fourth comparison. In the fourth comparison, analog input voltage Vin is higher than the selected comparison reference voltage VRB+9.5LSB.
Burns Doane Swecker & Mathis L.L.P.
Nguyen Khai
Renesas Technology Corp.
Tokar Michael
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