Analog-to-digital converter

Details Analog-to-digital converter Analog-to-digital converter

2003-01-23

2004-01-13

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

C341S159000

Reexamination Certificate

active

06677874

ABSTRACT:

BACKGROUND
This invention relates to analog-to-digital converters, and more particularly, to an analog-to-digital converter configured with virtual comparators to produce an increased number of output bits with relatively low hardware requirements.
Analog-to-digital converters are well known in the art. One type of analog-to-digital converter is a “successive approximation” converter. A successive approximation converter is configured to collect bits of information pertaining to the level of the input analog signal successively in time. Each individual collection of bits is compiled with the other collected bits to characterize the input signal to a desired accuracy or resolution determined by the analog-to-digital converter. Typically, a successive approximation converter uses a single comparator to derive a single bit of information at a time on each clock cycle. In operation, during each clock cycle, a single comparator compares the input signal to a single reference signal and provides one bit of information. That reference signal is then adjusted based on this one bit. On the second clock cycle, an additional bit is derived using the adjusted reference signal. This process is repeated for a predetermined number of clock cycles sufficient to provide the number of bits required for a digital output of a desired resolution and accuracy. The collected bits are then assembled at the end of the process to deliver a digital output with the desired resolution and accuracy of the converter.
Attempts have been made to create an effective analog-to-digital converter that can produce a digital output having n bits using less than 2
n
−1 comparators to do so. In one conventional example, an analog-to-digital converter purports to use less than 2
n
−1 comparators by employing a plurality of “pseudo-comparators”. These pseudo-comparators are placed between each pair of distantly-spaced actual comparators in order to generate interstitial outputs. These outputs are tailored to simulate the output of an actual comparator in that position based on weighted averages of the comparator outputs. Although such a circuit decreases the number of “primary” comparators on the input reference nodes, these pseudo-comparators are still actual discrete “hard-ware” elements in the converter circuitry. These elements exist at all times in fixed, predetermined and interpolative intervals, even though they are not actually connected to the input reference nodes. Thus, there is no real reduction in circuit elements. Another problem is that predetermined pseudo-comparator hardware elements are not variable, making them inflexible.
Therefore, there exists a need for a device and method for simultaneously collecting multiple bits of data but with relatively fewer circuit elements. As will be seen, the invention accomplishes this in an elegant manner.
SUMMARY OF INVENTION
The invention provides an analog-to-digital converter and related method where a plurality of comparators is arranged in a successive approximation manner. In operation, the converter is configured to selectively enable or disable the outputs from the individual comparators and sum the outputs together to produce a digital signal output. Furthermore, interpolated outputs may be derived by weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between actual comparators. Accordingly, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having a relatively larger number of bits using relatively few actual hardware elements for comparing signals.
Each of the plurality of comparators in the converter has additional inputs for a reference signal and/or an analog input signal. Each comparator further includes an input for an enablement signal and is configured to enable and disable the operation of a comparator in response to such a signal. Each comparator also includes components that produce a linear output in proportion to the enablement signal. Thus, according to the invention, a comparator output can be modified over a range by modifying the enablement signal by the desired proportions.
The invention also provides a method for converting an analog input signal into a digital signal in a successive approximation method to selectively enable or disable individual comparators over an input range and to sum the outputs of the comparators together. Virtual comparators can be created simply by varying the enabling signal to enable and disable comparators to varying degrees. Accordingly, the outputs of adjacent comparators together may be weighted and mixed together in proportions. This gives rise to virtual comparators created by operation of an interstitial output between the outputs of the actual comparators.


REFERENCES:
patent: 4596976 (1986-06-01), Mangelsdorf et al.
patent: 4965495 (1990-10-01), Wilber et al.
patent: 5017920 (1991-05-01), French
patent: 5291198 (1994-03-01), Dingwall et al.
patent: 5877720 (1999-03-01), Setty et al.

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