Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-06-24
2003-09-16
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S156000, C341S169000, C341S120000, C341S146000
Reexamination Certificate
active
06621442
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The invention is related to OFFSET-COMPENSATED SHARED PARALLEL ANALOG-TO-DIGITAL CONVERSION submitted as a separate application to the US PTO by the applicant of the present invention.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable
REFERENCE TO A MICROFICHE APPENDIX
Not applicable
BACKGROUND
1. Field of Invention
The invention relates to analog-to-digital (A/D) conversion via comparison of an analog input to a reference analog waveform, particularly to low-cost techniques using certain kinds of high-frequency non-linear waveforms such as sinusoidal waveforms.
2. Description of Prior Art
An analog-to-digital (A/D) converter provides a digital number as output given an analog input. Usually, there is a linear mapping between a partitioned range of allowed analog input values and an ordered set of allowed digital output values. The size of each bin in the partition depends on the total range of allowed analog input values and on the precision of the converter. Precision is often measured in terms of bits. High precision converters generally have much smaller bin sizes than low precision converters.
Speed is another important A/D converter feature. In a non-pipelined A/D converter, the conversion speed is the reciprocal of the total time required per conversion. High-speed converters are desirable in many applications. For instance, a high-speed A/D converter may allow digital processing at relatively high intermediate frequencies in communications systems such as wireless networks. As another example, a high-speed A/D converter might be used for A/D conversion of large numbers of sensor outputs in a digital still or video imaging system.
A difficulty with prior art A/D converters is that low-precision, high-speed A/D converters and high-precision, low-speed A/D converters have reasonable implementation cost, while high-speed, high-precision A/D converters do not.
Flash A/D converters are the fastest available. A flash converter has a set of comparators which simultaneously compare an analog input to a set of reference signals. The number of comparators grows exponentially with the number of bits of precision. Flash converters are typically limited to 8 to 10 bits of precision, at which point their component count becomes prohibitively large.
Another shortcoming of flash converters at 10 or more bits of precision is difficulty in matching the performance characteristics of the comparators. The bin sizes become small enough that such effects as comparator input offset voltage lead to missing codes—i.e. to digital outputs that can never occur—and to other unwanted distortions.
An alternative to flash conversion uses the basic technique of successive approximation (SA). In an SA A/D converter, a sequence of possible digital outputs is generated. Each sequence member is converted to an analog value, which is compared to an analog input. The comparison result is used to select a next member of the sequence.
The time required for SA A/D conversion increases at least linearly with the precision. While an SA A/D converter can be implemented as a pipeline in order to increase the conversion rate, the speed of each pipelined stage is still limited by the time required for settling of the digital-to-analog (D/A) converter which provides the analog reference signal corresponding to each selected possible digital output. SA A/D converters are often implemented with between 12 and 16 bits of precision.
For converters with very high precision—between 16 and 22 bits—techniques such as charge-balancing or multi-slope integration are used. In a charge-balancing converter, small packets of charge placed on a capacitor are selectively switched into a summing junction. A counter keeps track of the total number of charge packets switched into the summing junction during one conversion cycle, with the final count being the digital output. Charge-balancing techniques suffer from a long conversion cycle and are not amenable to shared parallel implementations.
Single-slope and dual-slope integration techniques are discussed in the second edition of THE ART OF ELECTRONICS by Paul Horowitz and Winfield Hill, with multi-slope integration techniques appearing in other prior art. The basic idea of these techniques is to generate analog reference waveforms made up of linear waveform segments, with the linear segments mapped to digital count sequences for an overall linear mapping between the range of allowed analog input values and the set of allowed digital output values.
For each linear segment, the time required for the difference between an unknown analog input level and a known reference signal to reach zero can be measured as a digital number representative of the unknown analog input. The linear segments can be reference ramp segments with a known slope, or can be input ramp segments with unknown slope. Reference ramp segments are desirable in the case of shared parallel A/D converters, as discussed in OFFSET-COMPENSATED SHARED PARALLEL ANALOG-TO-DIGITAL CONVERSION by the inventor of the present invention. In some multi-slope integrating A/D converters, signals can be selectively offset, so that, for instance, a ramp segment need not be generated over the full range of analog input values.
A linear ramp segment can be generated in an integrating A/D converter by charging or discharging a capacitor of known capacitance with a known constant current. The slope may be in error by a sufficient amount to cause unwanted distortion if the capacitance value or the current value are not known with sufficient precision. Such distortion can be corrected by taking ratios of multiple measurements to normalize with respect to unknown and/or slowly time-varying slope errors.
Another problem with generating a linear ramp segment with a constant current across a capacitor is dielectric absorption. Dielectric absorption—described in THE ART OF ELECTRONICS and in other prior art—occurs because the dielectric material between the plates of a capacitor is not a perfect insulator. The effects of the imperfection can be modeled by a parasitic capacitor and resistor connected in series with each other but in parallel with the desired ideal capacitor. Dielectric absorption depends on the charge stored on the ideal and parasitic portions of a capacitor, on the ideal and parasitic component values, and on the current flowing through the capacitor.
Dielectric absorption is principally a problem after changes in current flow. For instance, when a constant current is switched on to commence generation of a ramp segment, there is a transition period during which the actual voltage across the capacitor is a highly non-linear function of the constant current. After the transition period the voltage settles down and has a slope that is asymptotically linear.
Dielectric absorption creates a time window and a voltage range over which the result of the constant current is not a ramp segment of suitably accurate linearity. Dielectric absorption also results in a slope error in the steady state. The time window duration and the wasted voltage range depend on the values of the parasitic components, on the ideal capacitance, on the constant current value, and on the desired converter precision. For high-precision slope-based A/D converters, the charging current is usually small, resulting in a ramp of long duration. A long time window is allowed for the transition in exchange for a small wasted voltage range. The slope error can be corrected simultaneously with the slope error due to ideal capacitor or constant current value errors, as described in National Semiconductor Application Note 260, entitled A 20-BIT (1PPM) LINEAR SLOPE-INTEGRATING A/D CONVERTER.
The clear result of a ramp segment of long duration is a long A/D conversion time for each converted input. Including further time for full charging or discharging of the integrating capacitor prior to initiating ramp segment generation further decreases the conversion rate.
SUMMARY
The present invention enables low-cost,
Mai Lam T.
Tokar Michael
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