Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-07-12
2001-02-13
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S160000
Reexamination Certificate
active
06188347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to analog-to-digital converters, and more particularly to a system and method for minimizing sparkle codes.
2. Description of the Related Art
Analog-to-digital conversion is used to interface an electrical or electronic system using analog signals capable of continuous variation to an electronic system using discrete digital signals. The reverse operation of digital-to-analog conversion is also used.
FIG. 1
illustrates an embodiment of a typical prior art parallel analog-to-digital converter (ADC)
100
, also known as a flash converter. An analog input voltage signal (INPUT)
105
is input to a plurality of comparators
115
. A reference voltage signal (REF)
110
is also input to the plurality of comparators
115
through a voltage divider tree including a plurality of resistors
111
between the reference signal
110
and ground
112
. As shown, the positive input of each comparator
115
is the input signal
105
, and the negative input of each comparator
115
is a reference signal between REF
110
and ground
112
. The reference signal
110
applied to the negative input of each comparator
115
has a different voltage according to the voltage divider tree.
The output of each comparator
115
is typically input to a latch
120
. The output of each comparator
115
is stored in the respective latch
120
upon a rising edge of the clock signal (CLK)
125
. The collective outputs of the comparators
115
, stored in the latches
120
, are a thermometer code output
130
. The thermometer code
130
is input to a decoder
135
, sometimes referred to as an encoder. The decoder
135
decodes the thermometer code
130
into a multiple bit output
140
. The output
140
is a digital value corresponding to the input analog signal
105
.
A thermometer code
130
is typically a binary string of numbers, one binary value per comparator
115
. Assigning the convention of most significant bit (MSB) on the left and least significant bit (LSB) on the right, i.e. MSB to LSB, the thermometer code
130
represents the binary output string of the plurality of comparators
115
. The MSB is taken from the comparison between the input signal
105
and the reference signal
110
. The LSB is taken from the comparison between the input signal
105
and the ground
112
. In the thermometer code
130
, each successive digit of the code changes from a “0” to a “1” as value of the thermometer code increases. Assuming seven comparators, the thermometer code and the decoded output
140
could only be any one of the following:
Index
Thermometer Code
Decode
A
0000000
000
B
0000001
001
C
0000011
010
D
0000111
011
E
0001111
100
F
0011111
101
G
0111111
110
H
1111111
111
all other
unknown
Note that thermometer code A signifies an input signal
105
that is below one-seventh of the reference signal
110
. Thermometer code B signifies an input signal
105
that is above one-seventh of the reference signal
110
but below two-sevenths of the reference signal
110
. Thermometer code H signifies an input signal
105
that is above the reference signal
110
.
By convention, most ADCs
100
output the decode of thermometer code H as an error code since the output of the comparators
115
is other than an accepted value for a thermometer code
130
. Any value above the reference signal
110
is unmeasurable, i.e. there is no way to know how far above the reference signal
110
that the input signal is. An output that is not a proper thermometer code
130
is called a sparkle code, glitch or glitch error, or a misconversion error. For example, if the output of the comparators
115
were 0001011, then the decoder
135
would output an unknown code.
The reason for the error code output is that decoders
135
typically only look for the single transition from a “0” to a “1” in the thermometer code
130
. If two or more transitions occur, the decoder
135
cannot properly decode the thermometer code
130
, and hence the decoder
135
may output an incorrect or erroneous code. Incorrect thermometer codes can result from signal propagation delays in the circuit. For example, the output of the comparators
115
may be latched by the latches
120
at slightly different times, allowing for one latch
120
F to latch a “one” while latch
120
G latches a “zero”.
Therefore, an improved system and method for analog-to-digital conversion is desired that has reduced sparkle codes. The improved method of analog-to-digital conversion should have utility in many systems that use analog-to-digital conversion, such as sigma-delta (S/D) converters.
A sigma-delta converter
200
, such as that shown in
FIG. 2
, may include an ADC
100
such as that shown in FIG.
1
. Large numbers of error codes may cause problems in the multibit S/D converter
200
of FIG.
2
. It is noted that these devices are also referred to as delta-sigma converters and oversampled ADCs. As shown, S/D) converter
200
accepts an input signal V
in
into a summing node
205
. The output of the summing node
205
is filtered in a filter
210
, preferably a low pass filter, before being presented to the ADC
100
of FIG.
1
. The digital output
140
of the ADC
100
is the output of the sigma-delta converter
200
. The digital output
140
is also fed into digital-to-analog (DAC) converter
220
. The analog output of the DAC
220
is subtracted from the summing node
205
. This creates a feedback loop inside the sigma-delta converter
200
. It is noted that the addition or subtraction of the analog output of the DAC
220
in the summing node
205
is determined by the relative phase of the output of the comparators
115
in the ADC
100
.
The S/D converter
200
converts the analog input signal V
in
into a continuous stream of digital signals at the output at a rate determined by the clock rate of the clock CLK
125
, shown in FIG.
1
. Due to the nature of the negative feedback loop, the average value outputted by the DAC
220
approaches that of the input signal V
in
if the loop gain is sufficiently high.
If a relatively rapidly changing analog signal is input to the S/D converter
200
as the analog input signal V
in
, sparkle codes may generate a substantial amount of glitch energy, causing a loss of linearity. The bandwidth of the modulator also demands that the ADC
100
and DAC
220
take as little time as possible to process the analog-in and analog-out signals.
What is needed is an improved way to convert analog signals to digital signals in an analog-to-digital converter. The decode of the thermometer code
130
should be as close to the analog value as possible. Sigma-delta conversion should benefit from the low glitch energy of the improved ADC.
SUMMARY OF THE INVENTION
The present invention comprises a system and method for analog-to-digital conversion. The system comprises, in one embodiment, a plurality of comparators each coupled to receive an analog input signal, and an adder decoder coupled to receive the outputs of the comparators. Each comparator also receives a respective reference signal for comparison with the analog input signal. Each comparator is configured to output a digital value indicative of the comparison between the analog input signal and the respective reference signal. The adder decoder is configured to output a digital representation of the analog input signal based on the result and to add the digital output signals generated by the comparators. This system may advantageously provide for a more efficient way to convert analog signals to digital signals without the generation of sparkle codes.
In one embodiment, the adder decoder of the analog-to-digital comparator comprises a pyramid of adders. The first stage of the pyramid of adders may comprise 2-bit adders. Each additional stage of the pyramid of adders may comprise half as many n+1 bit adders as the n bit adders of the stage below. In one embodiment, the pyramid of adders is implemented in a programmable logic, preferably an FPGA.
Similarly, a method is also contemplated, comprising in one embod
Conley Rose & Tayon
Hood Jeffrey C.
National Instruments Corporation
Williams Howard L.
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