Analog-to-digital conversion method and device, in...

Details Analog-to-digital conversion method and device, in... Analog-to-digital conversion method and device, in...

2002-01-29

2004-01-06

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C714S768000, C365S185010

Reexamination Certificate

active

06674385

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an analog-to-digital conversion method in high-density multilevel non-volatile memory devices, being of the type wherein a reading operation is performed on a multilevel memory cell, comprising a floating gate transistor with drain and source terminals, by applying predetermined bias voltage values to its drain and source terminals while its drain terminal is applied a predetermined current value, and by measuring the value of its gate voltage.
The invention further relates to a device implementing the method.
2. Description of the Related Art
Known are multilevel memory devices which can store plural logic values in a single memory cell. Such devices are in the form of integrated electronic circuits, which have attained a sufficient degree of reliability to allow their manufacture in large volumes for a variety of technical and commercial applications.
Multilevel memory devices are in high demand on the market of semiconductor-integrated electronic devices for the reason that they afford an information storage density which is at least twice as high as that of two-level memory devices, for the same technology and area requirements.
In the light of these considerations, any efforts to develop memory devices that can store a larger number of bits per memory cell are well warranted.
However, this goal clashes with technical problems posed by the very increase in the number of bits stored in a single cell, and by the handling thereof. Also, multilevel memory devices are expected to perform comparably with two-level memory devices, and especially to exhibit the same synchronous and asynchronous access times, same read and program parallelism, and same program and erase speeds.
To best appreciate all the aspects of this invention, the main electrical characteristics of a multilevel memory device will be reviewed briefly herein below.
A different programmed state of a memory cell reflects in a different value of its threshold voltage Vth.
With a two-level cell, there can only be two values, respectively corresponding to a logic “0” and a logic “1”. In this operational context, the amount of information that can be stored is of one bit per cell.
By contrast, a multilevel memory cell can store a larger number of bits than one. From the electrical standpoint, this means that the threshold voltage can have more than two values. The amount of information that can be stored in a single multilevel cell increases according to the following relation:
n
bits/cell=log
2
(
n
values of
Vth
).
From a physical standpoint, the ability to alter the threshold voltage Vth, and hence to program the multilevel memory cell, is afforded by the floating gate structure of the transistor which comprises the memory cell. The gate region is isolated in D.C. but accessible through charge injection processes of the Channel Hot Electrons and/or the Fowler-Nordheim Tunneling Effect types.
These processes, when suitably controlled, allow the amount of charge which is caught within the floating gate to be modulated, so that the effect of the latter on the value of the threshold voltage Vth can be altered.
A major problem of multilevel memory handling is that, as the number of the possible programmed states increases, the gap &Dgr;Vth between consecutive threshold voltage values decreases dramatically, according to the following relation:
&Dgr;
Vth=&Dgr;Vtot/
(
n
values of
Vth
).
In fact, reliability factors forbid an expansion of the overall gap &Dgr;Vtot to accommodate the various programmed states beyond 5 to 6V. Furthermore, in view of all the process “spreads” likely to occur, the variations in the operational conditions of the memory device (i.e., supply voltage, temperature, etc.), and the accuracy of the programming processes, the threshold voltage levels are bound to vary somewhat on either sides of their nominal values. It is customary to indicate this situation in terms of different “distributions” of the individual programmed states, rather than “exact values” thereof.
This particular aspect reflects in further narrowing of the nominal gap &Dgr;Vth between adiacent programmed states, which requires the accuracy of the circuits concerned with reading the logic information from the cells to be augmented proportionally.
For example, with sixteen-level memory cells, that is cells capable of storing four bits each, the above considerations lead to estimating the actual gap &Dgr;Vth at around 200 mV. For typical current gains of the memory cells, on the order of 10 &mgr;A/V, the current difference between adjacent programmed states would be about 2 &mgr;A.
Under conditions such as these, the read circuitry that incorporates the sense amplifiers has great difficulty to discriminate between programmed states of the cell, unless the read time can be considerably extended, which would lead to degraded performance of the device as regards memory access time.
It should be further added that current-mode sensing schemes may “disturb” the programmed state of an addressed cell and result in progressive alteration of its threshold voltage Vth. This phenomenon is recognized as “read disturb” in the relevant literature. In fact, current-mode reading is achieved by maintaining, on the terminals of the addressed cell, definite bias conditions which are the same for all the cells and, therefore, unrelated to the cell programmed states. These conditions may be, for example: Vg=6 V; Vdrain=1 V; and Vsource=0 V.
In this way, the information contained in the addressed cell can be derived from the cell drain current.
However, these reading bias conditions lead to electric fields being developed between the conduction channel and the floating gate, which fields are the stronger the smaller is the value of the threshold voltage Vth. Unfortunately, these electric fields are sufficiently strong to significantly raise the probability of charge being injected into the floating gate. This phenomenon results in re-programming, as harmful as it is undesired, of the addressed cell and may strike unevenly, since its effectiveness is proportional to the difference between the read voltage Vg and the threshold voltage Vth.
The net outcome of all this is a progressive reduction of the gap &Dgr;Vth separating adjacent programmed states, with a consequent loss of reliability which will be the more significant the smaller the gep &Dgr;Vth and the larger the number of bits stored in each cell.
It should be considered, moreover, that current-mode reading is affected by the source resistance introducing non-linearity, to the point that the informational contents of a selected cell may be read erroneously.
In the light of the above considerations, the need of a circuit architecture which were effective to read from memory cells having n levels, e.g. sixteen levels, and ensured a read time of less than 100 ns, affording a memory access time on the order of 150 ns, can be fully appreciated.
It also appears from the foregoing considerations that the “current” mode reading approach is inadequate to meet the above requirement.
However, another method of reading the informational contents of a memory cell has been proposed in the art.
This prior approach is a “voltage” mode sensing method which allows the information stored in the cell to be retrieved by determining the cell threshold voltage Vth, or a voltage proportional thereto, usually the gate voltage Vg. In principle, the “voltage” sensing method consists of forcing a suitable drain current (Iref), concurrently with predetermined bias conditions, on the drain and source terminals of the cell (e.g., Vdrain=1 V and Vsource=0 V). These being the conditions for operation, the gate voltage produced by the cell, Vsenseout, is extracted.
This voltage Vsenseout becomes a function of the threshold voltage Vth once the drain current Iref and the current gain Gm of the cell are set, according to the following relation:
Vg=Vsenseout=Vth+Gn*Iref.
This value un

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