Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-06-18
2004-01-27
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000
Reexamination Certificate
active
06683554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog-to-digital conversion circuit having a multi-stage pipeline (multi-step flash) structure.
2. Description of the Background Art
In recent years, the demands for analog-to-digital conversion circuits (A/D converters) for processing video signals have increased with the progress of digital processing techniques for video signals. High-speed conversion operations are required for analog-to-digital conversion circuits for processing video signals. Conventionally, therefore, two-step flash (two-step parallel) systems have been widely used.
As the number of converted bits increases, however, sufficient conversion accuracy has not been obtained in the two-step flash systems. Therefore, analog-to-digital conversion circuits having multi-stage pipeline (step-flash) structures have been developed.
FIG. 38
is a block diagram showing the structure of a conventional analog-to-digital conversion circuit having a multi-stage pipeline structure. The analog-to-digital conversion circuit shown in
FIG. 38
has a 10-bit four-stage pipeline structure. The analog-to-digital conversion circuit is disclosed in JP-A-9-69777, for example.
In
FIG. 38
, the analog-to-digital conversion circuit
101
comprises a sample-and-hold circuit
102
, a first-stage circuit
103
, a second-stage circuit
104
, a third-stage circuit
105
, a fourth-stage circuit
106
, a plurality of latch circuits
107
, and an output circuit
108
.
Each of the first (initial)- to third-stage circuits
103
to
105
comprises a sub-A/D (Analog-to-Digital) converter
109
, a D/A (Digital-to-Analog) converter
110
, and a subtraction amplification circuit (a differential amplifier)
111
. The fourth (final)-stage circuit
106
comprises only a sub-A/D converter
109
.
The first-stage circuit
103
has a 4-bit configuration, and each of the second- to fourth-stage circuits
104
to
106
has a 2-bit configuration. In each of the first- to third-stage circuits
103
to
105
, the respective numbers of bits (bit configurations) of the sub-A/D converter
109
and the D/A converter
110
are set to the same value.
The operations of the analog-to-digital conversion circuit
101
will be then described. The sample-and-hold circuit
102
samples an analog input signal Vin, and holds the sampled analog input signal for a predetermined time period. The analog input signal Vin outputted from the sample-and-hold circuit
102
is transferred to the first-stage circuit
103
.
In the first-stage circuit
103
, the sub-A/D converter
109
subjects the analog input signal Vin to A/D (analog-to-digital) conversion. A digital output (
29
,
28
,
27
,
26
), which is the result of the A/D conversion by the sub-A/D converter
109
, is transferred to the D/A converter
110
, and is also transferred to the output circuit
108
through the four latch circuits
107
. The subtraction amplification circuit
111
amplifies the difference between the result of D/A (digital-to-analog) conversion by the D/A converter
110
and the analog input signal Vin. An output from the subtraction amplification circuit
111
is transferred to the second-stage circuit
104
.
The second-stage circuit
104
performs the same operations as those of the first-stage circuit
103
with respect to the output from the subtraction amplification circuit
111
in the first-stage circuit
103
. Further, the third-stage circuit
105
performs the same operations as those of the first-stage circuit
103
with respect to an output from the subtraction amplification circuit
111
in the second-stage circuit
104
. An intermediate high order 2-bit digital output (2
5
, 2
4
) is obtained from the second-stage circuit
104
, and an intermediate low order 2-bit digital output (2
3
, 2
2
) is obtained from the third-stage circuit
105
.
In the fourth-stage circuit
106
, the sub-A/D converter
109
subjects the output from the subtraction amplification circuit
111
in the third-stage circuit
105
to A/D conversion, thereby obtaining a low order 2-bit digital output (2
1
, 2
0
).
The digital outputs from the first- to fourth-stage circuits
103
to
106
simultaneously reach the output circuit
108
through the respective latch circuits
107
. That is, the latch circuits
107
are provided to synchronize the respective digital outputs from the circuits
103
to
106
with each other.
The output circuit
108
outputs a 10-bit digital output Dout of the analog input signal Vin in parallel after digital correction processing, when required.
In each of the first- to third-stage circuits
103
to
105
in the analog-to-digital conversion circuit
101
, the subtraction amplification circuit
111
amplifies the difference between the analog input signal Vin or the output from the subtraction amplification circuit
111
in the preceding stage of circuit
103
or
104
and the result of the D/A conversion of the digital output thereof.
Even if the number of converted bits increases to reduce the LSB (Least Significant Bit), therefore, the resolution of each of comparators constituting the sub-A/D converter
109
can be substantially improved, thereby obtaining sufficient conversion accuracy.
FIG. 39
is a circuit diagram of the sub-A/D converter
109
and the D/A converter
110
in the analog-to-digital conversion circuit
101
shown in FIG.
38
. The sub A/D converter
109
shown in
FIG. 39
is a total parallel comparison (flash) system sub-A/D converter, and the D/A converter
110
is a capacitance array system D/A converter.
The sub-A/D converter
109
comprises n resistors R and n comparators D
1
to Dn. All the resistors R have the same resistance value, and are connected in series between a node N
31
receiving a high-potential side reference voltage VRT and a node N
32
receiving a low-potential side reference voltage VRB. Let VR (
1
) to VR (n) respectively be potentials at nodes N
41
to N
4
n
among the n resistors R between the node N
32
and the node N
31
.
An input signal VI (the analog input signal Vin or the output from the subtraction amplification circuit
111
in the preceding stage of circuit
103
,
104
, or
105
) is inputted to positive input terminals of the comparators D
1
to Dn. Further, the potentials VR (
1
) to VR (n) at the nodes N
41
to N
4
n
are respectively applied to negative input terminals of the comparators D
1
to Dn.
Consequently, outputs from the comparators D
1
to Dn enter a high level, respectively, when the input signal VI is higher than the potentials VR (
1
) to VR (n), while entering a low level, respectively, when the input signal VI is lower than the potentials VR (
1
) to VR (n).
The D/A converter
110
comprises respective n switches E
1
to En, F
1
to Fn, G
1
to Gn, and H
1
to Hn, n positive-side capacitors B
1
to Bn, and n negative-side capacitors C
1
to Cn which are respectively connected to one another in an array shape.
All the capacitors B
1
to Bn and the capacitors C
1
to Cn have the same capacitance value c. A differential positive side output voltage VDA (+) is generated from one terminal (hereinafter referred to as an output terminal) of each of the capacitors B
1
to Bn, and a differential negative side output voltage VDA (−) is generated from one terminal (hereinafter referred to as an output terminal) of each of the capacitors C
1
to Cn. The other terminal of each of the capacitors B
1
to Bn and C
1
to Cn is referred to as an input terminal.
Respective one terminals of the switches E
1
to En are connected to the node N
31
, and the other terminals thereof are respectively connected to the input terminals of the capacitors B
1
to Bn. Respective one terminals of the switches F
1
to Fn are connected to the node N
31
, and the other terminals thereof are respectively connected to the input terminals of the capacitors C
1
to Cn. Respective one terminals of the switches G
1
to Gn are connected to the node N
32
, and the other terminals thereof are respectively connected to the input terminals of the capacitors B
1
to Bn
Kato Ken-ichi
Kimura Yasuyuki
Nikai Norihiro
Tani Kuniyuki
Wada Atsushi
Jean-Pierre Peguy
Sanyo Electric Co,. Ltd.
Westerman Hattori Daniels & Adrian LLP
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