Analog-to-digital conversion

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H03M 144

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active

046653821

ABSTRACT:
There is provided an analog-to-digital conversion technique that utilizes a sample and hold circuit for each bit try stage whereby after the most significant bit try, the remainder is sampled and held by the succeeding stage as an unknown input voltage for comparison with its respective reference voltage representing its corresponding bit weight. Thus, remainders for each bit weight comparison are successively passed from the most significant bit to the least significant bit as input voltages to the next bit try stage. The previous bit stage takes a new sample input voltage and starts another conversion at the next clock pulse. After the first full digital output of the initial conversion, a new digital output word of the successive sampled signal voltage is available after each clock pulse.

REFERENCES:
patent: 2876418 (1959-03-01), Villars
patent: 3500381 (1970-03-01), Conway
patent: 4326192 (1982-04-01), Merrill
patent: 4375059 (1983-02-01), Schlig
Martin "Conference Record of Fifteenth Asilomar Conference on Circuits Systems & Computers" Pacific Grove, Calif., Nov. 9-11, 1981, pp. 489-492.

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