Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-07-28
2002-09-10
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S189070
Reexamination Certificate
active
06449212
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-228710, Aug. 12, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to an analog synchronization circuit applied to a semiconductor storage device such as a synchronous DRAM or the like.
In a semiconductor storage device of this type, an internal clock signal generated inside the chip must be synchronized with an external clock signal supplied from a circuit outside the chip. In the chip, when an external clock signal is received by an input buffer, and the external clock signal, output from the input buffer is distributed inside the chip, the clock signals inside and outside the chip have different phases due to input buffer and line delays. To avoid such phase difference, various synchronization circuits for synchronizing external and internal clock signals have been developed.
As such synchronization circuits, for example, a mirror type DLL (DLL; Delay Locked Loop) including an SMD (Synchronous Mirror Delay) used in T. Saeki, et al. “A 2.5 ns Clock Access 250 MHz 256 Mb SDRAM with a Synchronous Mirror Delay”, ISSCC Digest of Technical Papers, pp. 374-375, Feb., 1996, an STBD (Synchronous Traced Backward Delay) described in U.S Pat. No. 5,867,432, and the like is known. The mirror type DLL has high synchronization speed, and can generate an internal clock signal which is synchronized with an external clock signal from the third clock of the external clock signal.
FIG. 27
shows an example of a conventional mirror type DLL. This mirror type DLL comprises an input buffer (I.B.), output buffer (O.B.), delay monitor (DM), and delay line (DL). The delay monitor (DM) is comprised of a replica circuit of an input buffer (I.B.) and output buffer (O.B.), and monitors their delay times. The delay line (DL) comprises a forward delay line DL
1
and backward delay line DL
2
. In this delay line (DL), the backward delay line attains synchronization by a mirror operation for delaying backward pulses by the same delay time as that of a forward pulse signal supplied to the forward delay line. For this reason, precision of making the delay times of the two delay lines equal to each other is a factor that largely determines synchronization precision.
The conventional delay line (DL) is constructed by connecting a plurality of logic gates such as inverter circuits and the like in series with each other. The delay time of the delay line is determined by the number of logic gate stages of the backward delay line DL
2
that the backward pulses pass through on the basis of information indicating the number of logic gate stages of the forward delay line DL
1
that the forward pulses pass through. In this manner, the delay time is defined by a quantized value, i.e., the number of logic gate stages.
For this reason, as shown in
FIG. 28
, the delay amount in the forward delay line does not equal that in the backward delay line, thus producing quantization errors.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made to solve the aforementioned problems, and has as its object to provide an analog synchronization circuit which can prevent any quantization errors, and can make the delay amounts of forward and backward pulses equal to each other.
The object of the present invention is achieved by the following apparatus.
An analog synchronization circuit comprises: a first capacitor; a first current source circuit for starting charging of the first capacitor in response to a first clock signal, the first current source circuit stopping charging in response to a second clock signal delayed behind the first clock signal; a second capacitor; a second current source circuit for starting charging of the second capacitor in response to the second clock signal; and a comparator for comparing voltages of the first and second capacitors and generating a timing signal when the two voltages match.
The object of the present invention is achieved by the following apparatus.
An analog synchronization circuit comprises: a first capacitor; a first current source circuit for starting charging of the first capacitor in response to a first clock signal, the first current source circuit stopping charging in response to a second clock signal delayed n clocks behind the first clock signal; a second capacitor; a second current source circuit for starting charging of the second capacitor in response to the second clock signal, the second current source circuit having a current amount n times a current amount of the first current source circuit; and a comparator for comparing voltages of the first and second capacitors, the comparator generating a timing signal when charged voltages of the first and second capacitors match.
The object of the present invention is achieved by the following apparatus.
An analog synchronization circuit comprises: a first capacitor; a first current source circuit for starting charging of the first capacitor in response to a first clock signal, the first-current source circuit stopping charging in response to a second clock signal delayed n clocks behind the first clock signal; a second capacitor having a capacitance 1
a capacitance of the first capacitor; a second current source circuit for starting charging of the second capacitor in response to the second clock signal; and a comparator for comparing voltages of the first and second capacitors, the comparator generating a timing signal when charged voltages of the first and second capacitors match.
The object of the present invention is achieved by the following apparatus.
An analog synchronization circuit comprises: a first capacitor; a first current source circuit for starting charging of the first-capacitor in response to a first clock signal, the first current source circuit divisionally charging the first capacitor by 1
from the first clock signal, and stopping charging in response to a second clock signal delayed n clocks behind the first clock signal; a second capacitor; a second current source circuit for starting charging of the second capacitor in response to the second clock signal, the second current source circuit having a current amount n times a current amount of the first current source circuit; and a comparator for comparing voltages of the first and second capacitors, the comparator generating a timing signal when charged voltages of the first and second capacitors match.
According to the present invention, the delay time can be detected as an analog amount, i.e., a charge amount. For this reason, generation of quantization errors as a problem in the conventional mirror type DLL using the logic gates in the delay line can be prevented. Hence, an analog synchronization circuit that can make the delay amounts of forward and backward pulses equal to each other can be provided.
Since the capacitor is charged by a constant current source, the influences of power supply voltage drifts can be removed, and the operation margin can be improved.
Furthermore, clock signals produce noise upon traveling through the logic gates. However, since a constant current source circuit is used, AC components can be greatly reduced. For this reason, generation of noise can be remarkably suppressed.
Since external clock signals are averaged in an analog manner, jitter of the external clock signals can be suppressed. In addition, since external clock signals are averaged in an analog manner, generation of quantization errors upon averaging can also be prevented.
Furthermore, since the comparator uses an inverter circuit, the input and output terminals of which are short-circuited upon initialization, and which receives two voltages to be compared via the capacitor, a high-sensitivity comparator can be formed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Th
Akita Hironobu
Isobe Katsuaki
Toda Haruki
Banner & Witcoff , Ltd.
Elms Richard
Nguyen Tuan T.
LandOfFree
Analog synchronization circuit for synchronizing external... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Analog synchronization circuit for synchronizing external..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Analog synchronization circuit for synchronizing external... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2883960