Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-11-08
2001-12-25
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S284000, C327S161000
Reexamination Certificate
active
06333658
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-324202, filed Nov. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to an analog synchronization circuit which is provided in a semiconductor memory device, such as a synchronous DRAM, and generates, from an external clock signal, an internal clock signal synchronous with this external clock signal.
This type of semiconductor memory device requires that the internal clock signal generated inside a chip should be synchronized with an external clock signal supplied from outside the chip. When the external clock signal is received at an input buffer in the chip and is distributed inside the chip, the phase of the clock signal inside the chip differs from the phase of the clock signal outside the chip due to delays made by buffers and lines. To avoid this shortcoming, various synchronization circuits which synchronize the internal clock signal with the external clock signal have been developed.
As such synchronization circuits, there are mirror type DLLs (Delay Locked Loops) which include an SMD (Synchronous Mirror Delay) used in, for example, “A 2.5 ns Clock Access 250 MHz 256 Mb SDRAM with a Synchronous Mirror Delay” by T. Saeki, et al., ISSCC Digest of Technical Papers, pp. 374-375, February 1996, and an STBD (Synchronous Traced Backward Delay) described in the U.S. Pat. Nos. 5,867,432, 5,986,949, and 6,034,901. The mirror type DLL has a fast synchronization speed and can generate an internal clock signal synchronous with an external clock signal from the third clock of the external clock signal.
FIG. 1
shows one example of a conventional mirror type DLL. This mirror type DLL comprises an input buffer IB, an output buffer OB, a delay monitor DM which is a replica circuit of those buffers, and a delay line DL. The delay line DL comprises a forward pulse delay line DL
1
and a backward pulse delay line DL
2
, and a analog synchronization operation is carried out by a mirror operation which reflects the delay time on the forward pulse delay line DL
1
onto the backward pulse delay line DL
2
. An important factor in determining the synchronization precision is how to accurately make the delay times on both delay lines equal to each other.
The conventional delay line DL is constituted by connecting a plurality of logic gates, such as inverter circuits, in series. The delay time on the delay line is determined by how many stages of logic gates, which constitute the backward pulse delay line DL
2
, a backward pulse passes based on information on how many stages of logic gates, which constitute the forward pulse delay line DL
1
, a forward pulse has passed. Apparently, the delay time becomes a quantized quantity which is the number of stages of logic gates.
As shown in
FIG. 2
, therefore, the amount of delay on the forward pulse delay line does not become equal to the amount of delay on the backward pulse delay line, thus generating a quantization error.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an analog synchronization circuit which can prevent the generation of a quantization error and can make the delay amount of a forward pulse substantially equal to the delay amount of a backward pulse.
To achieve the above object, according to one aspect of this invention, there is provided an analog synchronization circuit which comprises a first capacitor; a first current source circuit for starting charging the first capacitor in accordance with a first clock signal and stopping the charging in accordance with a second clock signal delayed from the first clock signal; a second capacitor; a second current source circuit for starting charging the second capacitor in accordance with the second clock signal; and a comparator circuit for comparing charge voltages of the first and second capacitors with each other and generating a timing signal when the charge voltages coincide with each other, and in which the comparator circuit includes a first switch having one end supplied with the charge voltage of the first capacitor, a second switch having one end supplied with the charge voltage of the second capacitor and the other end connected to the other end of the first switch, a third capacitor having one end connected to a common node between the other ends of the first and second switches, a first amplifier circuit having an input node connected to the other end of the third capacitor and an output node from which the timing signal is output, and a third switch for controlling supply of a voltage equivalent to a threshold voltage of the first amplifier circuit to the other end of the third capacitor, wherein when the first and third switches are enabled, the second switch is controlled to be disabled, and when the second switch is enabled, the first and third switches are controlled to be disabled.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 3906247 (1975-09-01), Heffner
patent: 4736118 (1988-04-01), Fischer
patent: 5015892 (1991-05-01), Parsi et al.
patent: 5867432 (1999-02-01), Toda
patent: 5955905 (1999-09-01), Idei et al.
patent: 5986949 (1999-11-01), Toda
patent: 6034901 (2000-03-01), Toda
patent: 6069508 (2000-05-01), Takai
patent: 6121811 (2000-09-01), Scott et al.
patent: 6194937 (2001-02-01), Minami
T. Saeki, et al., “A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay”, ISSCC Digest of Technical Papers, pp. 374-375, Feb. 1996.
D. Shim, et al., “An Analog Synchronous Mirror Delay for High-Speed DRAM Application”, IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999.
U.S. application No. 09/628,449, filed Jul. 28, 2000; entitled “Analog Synchronization Circuit for Synchronizing External and Internal Clock Signals” to Haruki Toda, et al.
Akita Hironobu
Eto Satoshi
Isobe Katsuaki
Toda Haruki
Wada Masaharu
Banner & Witcoff , Ltd.
Callahan Timothy P.
Kabushiki Kaisha Toshiba
Nguyen Hai L.
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