Analog switch with minimized noise ascribable to gate capacitanc

Details Analog switch with minimized noise ascribable to gate capacitanc Analog switch with minimized noise ascribable to gate capacitanc

1988-08-09

1990-10-09

Mintel, William

357 41, 357 239, 357 45, 350333, 350332, 350334, 350335, 350336, H01L 2702

Patent

active

049624130

ABSTRACT:
An analog switch includes n-channel and p-channel MOSFETs formed in a surface of a semiconductor substrate. Each of the n-channel and p-channel MOSFETs has first, second and third diffused regions which are formed in the semiconductor surface with the width thereof substantially equal to each other. The first and third diffused regions are spaced from the second diffused region to form first and second channel regions, respectively. Each of the n-channel and p-channel MOSFETs has first and second gate electrodes which are interconnected in common to each other and placed on respective gate insulating layers overlaying the first and second channel regions, respectively. The first gate electrode has an end portion extending over part of the second diffused region by a predetermined length, while the second gate electrode has an end portion extending over another part, opposite to the earlier-mentioned part, of the second diffused region by a predetermined length. A sample and hold circuit including the analog switch is also provided.

REFERENCES:
patent: 3936676 (1976-02-01), Fujita
patent: 4345366 (1982-08-01), Brower
patent: 4391650 (1983-07-01), Pfeifer et al.
No Author, "MOS Moves onto High-Speed Track," Electronics, May 26, 1969, pp. 49-52.
Bower, "MOS Field Effect Transistors Formed by Gate Masked Ion Implantation," IEEE Transactions on Electron Devices, vol. Ed-15, No. 10, Oct. 1968, pp. 757-761.

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